/* PCI.c - PCI functions *//* Copyright - Galileo technology. */#include <common.h>#include <pci.h>#include <galileo/pci.h>static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {#ifdef CONFIG_ZUMA_V2	{0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},	{0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}#else				/* EVB??? This is a guess */	{0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},	{0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}#endif};static const unsigned int pci_p2p_configuration_reg[] = {	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION};static const unsigned int pci_configuration_address[] = {	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS};static const unsigned int pci_configuration_data[] = {	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER};static const unsigned int pci_error_cause_reg[] = {	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE};static const unsigned int pci_arbiter_control[] = {	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL};static const unsigned int pci_snoop_control_base_0_low[] = {	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW};static const unsigned int pci_snoop_control_top_0[] = {	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0};static const unsigned int pci_access_control_base_0_low[] = {	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW};static const unsigned int pci_access_control_top_0[] = {	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0};static const unsigned int pci_scs_bank_size[2][4] = {	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}};static const unsigned int pci_p2p_configuration[] = {	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION};static unsigned int local_buses[] = { 0, 0 };/********************************************************************* pciWriteConfigReg - Write to a PCI configuration register*                    - Make sure the GT is configured as a master before writing*                      to another device on the PCI.*                    - The function takes care of Big/Little endian conversion.*** Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec*                   (or any other PCI device spec)*           pciDevNum: The device number needs to be addressed.**  Configuration Address 0xCF8:**       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number*  |congif|Reserved|  Bus |Device|Function|Register|00|*  |Enable|        |Number|Number| Number | Number |  |    <=field Name**********************************************************************/void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,			unsigned int pciDevNum, unsigned int data){	volatile unsigned int DataForAddrReg;	unsigned int functionNum;	unsigned int busNum = PCI_BUS (pciDevNum);	unsigned int addr;	if (pciDevNum > 32)	/* illegal device Number */		return;	if (pciDevNum == SELF) {	/* configure our configuration space. */		pciDevNum =			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &			0x1f;		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &			0xff0000;	}	functionNum = regOffset & 0x00000700;	pciDevNum = pciDevNum << 11;	regOffset = regOffset & 0xfc;	DataForAddrReg =		(regOffset | pciDevNum | functionNum | busNum) | BIT31;	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);	GT_REG_READ (pci_configuration_address[host], &addr);	if (addr != DataForAddrReg)		return;	GT_REG_WRITE (pci_configuration_data[host], data);}/********************************************************************* pciReadConfigReg  - Read from a PCI0 configuration register*                    - Make sure the GT is configured as a master before reading*                     from another device on the PCI.*                   - The function takes care of Big/Little endian conversion.* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI*                        spec)*           pciDevNum: The device number needs to be addressed.* RETURNS: data , if the data == 0xffffffff check the master abort bit in the*                 cause register to make sure the data is valid**  Configuration Address 0xCF8:**       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number*  |congif|Reserved|  Bus |Device|Function|Register|00|*  |Enable|        |Number|Number| Number | Number |  |    <=field Name**********************************************************************/unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,			       unsigned int pciDevNum){	volatile unsigned int DataForAddrReg;	unsigned int data;	unsigned int functionNum;	unsigned int busNum = PCI_BUS (pciDevNum);	if (pciDevNum > 32)	/* illegal device Number */		return 0xffffffff;	if (pciDevNum == SELF) {	/* configure our configuration space. */		pciDevNum =			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &			0x1f;		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &			0xff0000;	}	functionNum = regOffset & 0x00000700;	pciDevNum = pciDevNum << 11;	regOffset = regOffset & 0xfc;	DataForAddrReg =		(regOffset | pciDevNum | functionNum | busNum) | BIT31;	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);	GT_REG_READ (pci_configuration_address[host], &data);	if (data != DataForAddrReg)		return 0xffffffff;	GT_REG_READ (pci_configuration_data[host], &data);	return data;}/********************************************************************* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where*                               the agent is placed on another Bus. For more*                               information read P2P in the PCI spec.** Inputs:   unsigned int regOffset - The register offset as it apears in the*           GT spec (or any other PCI device spec).*           unsigned int pciDevNum - The device number needs to be addressed.*           unsigned int busNum - On which bus does the Target agent connect*                                 to.*           unsigned int data - data to be written.**  Configuration Address 0xCF8:**       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number*  |congif|Reserved|  Bus |Device|Function|Register|01|*  |Enable|        |Number|Number| Number | Number |  |    <=field Name**  The configuration Address is configure as type-I (bits[1:0] = '01') due to*   PCI spec referring to P2P.**********************************************************************/void pciOverBridgeWriteConfigReg (PCI_HOST host,				  unsigned int regOffset,				  unsigned int pciDevNum,				  unsigned int busNum, unsigned int data){	unsigned int DataForReg;	unsigned int functionNum;	functionNum = regOffset & 0x00000700;	pciDevNum = pciDevNum << 11;	regOffset = regOffset & 0xff;	busNum = busNum << 16;	if (pciDevNum == SELF) {	/* This board */		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;	} else {		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |			BIT31 | BIT0;	}	GT_REG_WRITE (pci_configuration_address[host], DataForReg);	if (pciDevNum == SELF) {	/* This board */		GT_REG_WRITE (pci_configuration_data[host], data);	} else {		/* configuration Transaction over the pci. */		/* The PCI is working in LE Mode So it swap the Data. */		GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));	}}/********************************************************************* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where*                               the agent target locate on another PCI bus.*                             - Make sure the GT is configured as a master*                               before reading from another device on the PCI.*                             - The function takes care of Big/Little endian*                               conversion.* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI*                        spec). (configuration register offset.)*           pciDevNum: The device number needs to be addressed.*           busNum: the Bus number where the agent is place.* RETURNS: data , if the data == 0xffffffff check the master abort bit in the*                 cause register to make sure the data is valid**  Configuration Address 0xCF8:**       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number*  |congif|Reserved|  Bus |Device|Function|Register|01|*  |Enable|        |Number|Number| Number | Number |  |    <=field Name**********************************************************************/unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,					 unsigned int regOffset,					 unsigned int pciDevNum,					 unsigned int busNum){	unsigned int DataForReg;	unsigned int data;	unsigned int functionNum;	functionNum = regOffset & 0x00000700;	pciDevNum = pciDevNum << 11;	regOffset = regOffset & 0xff;	busNum = busNum << 16;	if (pciDevNum == SELF) {	/* This board */		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;	} else {		/* agent on another bus */		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |			BIT0 | BIT31;	}	GT_REG_WRITE (pci_configuration_address[host], DataForReg);	if (pciDevNum == SELF) {	/* This board */		GT_REG_READ (pci_configuration_data[host], &data);		return data;	} else {		/* The PCI is working in LE Mode So it swap the Data. */		GT_REG_READ (pci_configuration_data[host], &data);		return WORD_SWAP (data);	}}/********************************************************************* pciGetRegOffset - Gets the register offset for this region config.** INPUT:   Bus, Region - The bus and region we ask for its base address.* OUTPUT:   N/A* RETURNS: PCI register base address*********************************************************************/static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region){	switch (host) {	case PCI_HOST0:		switch (region) {		case PCI_IO:			return PCI_0I_O_LOW_DECODE_ADDRESS;		case PCI_REGION0:			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;		case PCI_REGION1:			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;		case PCI_REGION2:			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;		case PCI_REGION3:			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;		}	case PCI_HOST1:		switch (region) {		case PCI_IO:			return PCI_1I_O_LOW_DECODE_ADDRESS;		case PCI_REGION0:			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;		case PCI_REGION1:			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;		case PCI_REGION2:			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;		case PCI_REGION3:			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;		}	}	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;}static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region){	switch (host) {	case PCI_HOST0:		switch (region) {		case PCI_IO:			return PCI_0I_O_ADDRESS_REMAP;		case PCI_REGION0:			return PCI_0MEMORY0_ADDRESS_REMAP;		case PCI_REGION1:			return PCI_0MEMORY1_ADDRESS_REMAP;		case PCI_REGION2:			return PCI_0MEMORY2_ADDRESS_REMAP;		case PCI_REGION3:			return PCI_0MEMORY3_ADDRESS_REMAP;		}	case PCI_HOST1:		switch (region) {		case PCI_IO:			return PCI_1I_O_ADDRESS_REMAP;		case PCI_REGION0:			return PCI_1MEMORY0_ADDRESS_REMAP;		case PCI_REGION1:			return PCI_1MEMORY1_ADDRESS_REMAP;		case PCI_REGION2:			return PCI_1MEMORY2_ADDRESS_REMAP;		case PCI_REGION3:			return PCI_1MEMORY3_ADDRESS_REMAP;		}	}	return PCI_0MEMORY0_ADDRESS_REMAP;}bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,		  unsigned int bankBase, unsigned int bankLength){	unsigned int low = 0xfff;	unsigned int high = 0x0;	unsigned int regOffset = pciGetRegOffset (host, region);	unsigned int remapOffset = pciGetRemapOffset (host, region);	if (bankLength != 0) {		low = (bankBase >> 20) & 0xfff;		high = ((bankBase + bankLength) >> 20) - 1;	}	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */	GT_REG_WRITE (regOffset + 8, high);	if (bankLength != 0) {	/* must do AFTER writing maps */		GT_REG_WRITE (remapOffset, remapBase >> 20);	/* sorry, 32 bits only.								   dont support upper 32								   in this driver */	}	return true;}unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region){	unsigned int low;	unsigned int regOffset = pciGetRegOffset (host, region);	GT_REG_READ (regOffset, &low);	return (low & 0xfff) << 20;}unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region){	unsigned int low, high;	unsigned int regOffset = pciGetRegOffset (host, region);	GT_REG_READ (regOffset, &low);	GT_REG_READ (regOffset + 8, &high);	high &= 0xfff;	low &= 0xfff;	if (high <= low)