#pragma NOIV               // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
//   File:      bulkext.c
//   Contents:   Hooks required to implement USB peripheral function.
//
//   performs loopback on EP2OUT->EP6IN and EP4OUT->EP8IN
//   this code uses the external auto pointers to first move the data
//   to external RAM (0x2800) before looping back to the IN endpoint.
//
//   Copyright (c) 2000 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"  // SYNCDELAY macro

#define LED_ADDR		0x21

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings


extern BYTE	num;

//-----------------------------------------------------------------------------
// Task Dispatcher hooks
//   The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------

void TD_Init(void)             // Called once at startup
{
   // set the CPU clock to 48MHz
   CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   // set the slave FIFO interface to 48MHz
   IFCONFIG |= 0x40;

  // Registers which require a synchronization delay, see section 15.14
  // FIFORESET        FIFOPINPOLAR
  // INPKTEND         OUTPKTEND
  // EPxBCH:L         REVCTL
  // GPIFTCB3         GPIFTCB2
  // GPIFTCB1         GPIFTCB0
  // EPxFIFOPFH:L     EPxAUTOINLENH:L
  // EPxFIFOCFG       EPxGPIFFLGSEL
  // PINFLAGSxx       EPxFIFOIRQ
  // EPxFIFOIE        GPIFIRQ
  // GPIFIE           GPIFADRH:L
  // UDMACRCH:L       EPxGPIFTRIG
  // GPIFTRIG
  
  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
  //      ...these have been replaced by GPIFTC[B3:B0] registers

  // default: all endpoints have their VALID bit set
  // default: TYPE1 = 1 and TYPE0 = 0 --> BULK  
  // default: EP2 and EP4 DIR bits are 0 (OUT direction)
  // default: EP6 and EP8 DIR bits are 1 (IN direction)
  // default: EP2, EP4, EP6, and EP8 are double buffered

  // we are just using the default values, yes this is not necessary...
  EP1OUTCFG = 0xA0;
  EP1INCFG = 0xA0;
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA2;
  SYNCDELAY;                    
  EP4CFG = 0xA0;
  SYNCDELAY;                    
  EP6CFG = 0xE2;
  SYNCDELAY;                    
  EP8CFG = 0xE0;

  // out endpoints do not come up armed
  
  // since the defaults are double buffered we must write dummy byte counts twice
  SYNCDELAY;                    
  EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
  SYNCDELAY;                    
  EP2BCL = 0x80;
  SYNCDELAY;                    
  EP4BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
  SYNCDELAY;                    
  EP4BCL = 0x80;    

  // enable dual autopointer feature
  AUTOPTRSETUP |= 0x01;

  Rwuen = TRUE;                 // Enable remote-wakeup
  EZUSB_InitI2C();			// Initialize EZ-USB I2C controller
  //EZUSB_WriteI2C(0x21, 0x01, &(Digit[9]));
  //EZUSB_WaitForEEPROMWrite(0x21);

}


void TD_InitSlaveFIFO(void)
{
	// set the CPU clock to 48MHz
   	CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

	EP1OUTCFG = 0xA0;
  	EP1INCFG = 0xA0;
  	SYNCDELAY;  

	//first,do common config for all endpoint and FIFOS

	//CAUTION:if REVCTL is set to 0x03 as "Cypress highly recommends",
	//the board pending all the request from controle panel.
	//Ye Guodong 2004.4.28
	REVCTL = 0x00;//must set REVCTL.0 and .1 to 1
	SYNCDELAY;
	FIFORESET = 0x80;//reset all fifos
	SYNCDELAY;
	FIFORESET = 0x02;
	SYNCDELAY;
	FIFORESET = 0x04;
	SYNCDELAY;
	FIFORESET = 0x06;
	SYNCDELAY;
	FIFORESET = 0x08;
	SYNCDELAY;
	FIFORESET = 0x00;
	SYNCDELAY;
	IFCONFIG |= 0x43;//use IFCLK pin driven by external logic
	SYNCDELAY;		//use slave fifo interface pin driven sync by external master
	PINFLAGSAB = 0x00;//define: FLAGA as prog-level flag,FLAGB as full flag,
	SYNCDELAY;		//FLAGC as empty flag,no use FLAGD
	PINFLAGSCD = 0x00;
	PORTACFG = 0x00;//use PA7 as port pin ,not FIFO flag
	FIFOPINPOLAR = 0x00;//set all slave FIFO interface pins as active low
	SYNCDELAY;

	//then config EP8 as follow:
	EP8FIFOCFG = 0x0D;//this lets FX2 auto cnmmit IN packet, gives the ability to
					//to send zero lenth packets, ande sets the slave FIFO data
					// interface to 16-bits 
	EP8CFG = 0xE0;//set EP8 valid for IN's ,512 byte packets and 2x bufferred
	EP8AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
	SYNCDELAY;
	EP8AUTOINLENL = 0x00; 
	SYNCDELAY;
	EP8FIFOPFH = 0x82;
	SYNCDELAY;
	EP8FIFOPFL = 0x00;

	// config EP6  same as endpoint8:
	EP6FIFOCFG = 0x0D;//this lets FX2 auto cnmmit IN packet, gives the ability to
					//to send zero lenth packets, ande sets the slave FIFO data
					// interface to 16-bits 
	EP6CFG = 0xE2;//set EP6 valid for IN's ,512 byte packets and 2x bufferred
	SYNCDELAY;
	EP6AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
	SYNCDELAY;
	EP6AUTOINLENL = 0x00; 
	SYNCDELAY;
	EP6FIFOPFH = 0x82;
	SYNCDELAY;
	EP6FIFOPFL = 0x00;
	
	// config EP4 as follow:
	EP4FIFOCFG = 0x15;//this lets FX2 auto cnmmit OUT packet, gives the ability to
					//to send zero lenth packets, ande sets the slave FIFO data
					// interface to 16-bits 
	EP4CFG = 0xA0;//set EP4 valid for OUT's ,512 byte packets and 2x bufferred
	EP4AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
	SYNCDELAY;
	EP4AUTOINLENH = 0x00; 
	SYNCDELAY;
	EP4FIFOPFH = 0x82;
	SYNCDELAY;
	EP4FIFOPFL = 0x00;

	// config EP2  the same as endpoint4:
	EP2FIFOCFG = 0x15;//this lets FX2 auto cnmmit OUT packet, gives the ability to
					//to send zero lenth packets, ande sets the slave FIFO data
					// interface to 16-bits 
					SYNCDELAY;
	EP2CFG = 0xA2;//set EP2 valid for OUT's ,512 byte packets and 2x bufferred
	EP2AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
	SYNCDELAY;
	EP2AUTOINLENH = 0x00; 
	SYNCDELAY;
	EP2FIFOPFH = 0x82;
	SYNCDELAY;
	EP2FIFOPFL = 0x00;

	//finally,,manually arm the two OUT endpoint 
	SYNCDELAY;                    
  	//EP2BCL = 0x80;                // arm EP2OUT by writing byte count w/skip.
  	SYNCDELAY;                    
  	//EP2BCL = 0x80;
  	SYNCDELAY;                    
  	//EP4BCL = 0x80;                // arm EP4OUT by writing byte count w/skip.
  	SYNCDELAY;                    
  	//EP4BCL = 0x80;

	// enable dual autopointer feature
  	AUTOPTRSETUP |= 0x01;

  	Rwuen = TRUE;                 // Enable remote-wakeup
  	EZUSB_InitI2C();			// Initialize EZ-USB I2C controller


}

void TD_Poll(void)              // Called repeatedly while the device is idle
{
  WORD i;
  WORD count;
//	EZUSB_WriteI2C(0x21, 0x01, &(Digit[num]));
//	EZUSB_WaitForEEPROMWrite(0x21);


  if(!(EP2468STAT & bmEP2EMPTY))
  { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
     if(!(EP2468STAT & bmEP6FULL))
     {  // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
        // Source is EP2OUT
        APTR1H = MSB( &EP2FIFOBUF );
        APTR1L = LSB( &EP2FIFOBUF );

        // Destination is external RAM (at 0x2800)
        AUTOPTRH2 = 0x28;
        AUTOPTRL2 = 0x00;


       

        count = (EP2BCH << 8) + EP2BCL;

        for( i = 0x0000; i < count; i++ )
        {
           EXTAUTODAT2 = EXTAUTODAT1;
        }

        // Source is external RAM
        APTR1H = 0x28;
        APTR1L = 0x00;

        // Destination is EP6IN
        AUTOPTRH2 = MSB( &EP6FIFOBUF );
        AUTOPTRL2 = LSB( &EP6FIFOBUF );

        count = (EP2BCH << 8) + EP2BCL;

        for( i = 0x0000; i < count; i++ )
        {
           EXTAUTODAT2 = EXTAUTODAT1;
        }

        EP6BCH = EP2BCH;  
        SYNCDELAY;  
        EP6BCL = EP2BCL;        // arm EP6IN
        SYNCDELAY;                    
        EP2BCL = 0x80;          // re(arm) EP2OUT
     }
  }

  if(!(EP2468STAT & bmEP4EMPTY))
  { // check EP4 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
     if(!(EP2468STAT & bmEP8FULL))
     {  // check EP8 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
        // setup AUTOPOINTER(s) in SFR space
        // source is EP4OUT
        APTR1H = MSB( &EP4FIFOBUF );
        APTR1L = LSB( &EP4FIFOBUF );

        // Destination is external RAM (at 0x2A00)
        AUTOPTRH2 = 0x2A;
        AUTOPTRL2 = 0x00;

        count = (EP4BCH << 8) + EP4BCL;

        for( i = 0x0000; i < count; i++ )
        {
           EXTAUTODAT2 = EXTAUTODAT1;
        }

        // Source is external RAM
        APTR1H = 0x2A;
        APTR1L = 0x00;

        // Destination is EP8IN
        AUTOPTRH2 = MSB( &EP8FIFOBUF );;
        AUTOPTRL2 = LSB( &EP8FIFOBUF );;

        count = (EP4BCH << 8) + EP4BCL;

        // loop EP2OUT buffer data to EP6IN
        for( i = 0x0000; i < count; i++ )
        {
           // setup to transfer EP2OUT buffer to EP6IN buffer using AUTOPOINTER(s)
           EXTAUTODAT2 = EXTAUTODAT1;
        }

        EP8BCH = EP4BCH;  
        SYNCDELAY;  
        EP8BCL = EP4BCL;        // arm EP8IN
        SYNCDELAY;                    
        EP4BCL = 0x80;          // re(arm) EP4OUT
     }
  }
}

BOOL TD_Suspend(void)          // Called before the device goes into suspend mode
{
   return(TRUE);
}

BOOL TD_Resume(void)          // Called after the device resumes
{
   return(TRUE);
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------

BOOL DR_GetDescriptor(void)
{
   return(TRUE);
}

BOOL DR_SetConfiguration(void)   // Called when a Set Configuration command is received
{
   Configuration = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received
{
   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_SetInterface(void)       // Called when a Set Interface command is received
{
   AlternateSetting = SETUPDAT[2];
   return(TRUE);            // Handled by user code
}

BOOL DR_GetInterface(void)       // Called when a Set Interface command is received
{
//  EZUSB_WriteI2C(0x21, 0x01, &(Digit[8]));
 // EZUSB_WaitForEEPROMWrite(0x21);
   EP0BUF[0] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);            // Handled by user code
}

BOOL DR_GetStatus(void)
{
   return(TRUE);
}

BOOL DR_ClearFeature(void)
{
   return(TRUE);
}

BOOL DR_SetFeature(void)
{
   return(TRUE);
}

BOOL DR_VendorCmnd(void)
{
   return(TRUE);
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
 // EZUSB_InitI2C();

  
//		EZUSB_WriteI2C(0x21, 0x01, &(Digit[num]));
//  		EZUSB_WaitForEEPROMWrite(0x21);
		
   GotSUD = TRUE; 
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUDAV;         // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUTOK;         // Clear SUTOK IRQ
}

void ISR_Sof(void) interrupt 0
{
 // EZUSB_WriteI2C(0x21, 0x01, &(Digit[8]));
  //EZUSB_WaitForEEPROMWrite(0x21);// Set flag
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSOF;            // Clear SOF IRQ
}

void ISR_Ures(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmURES;         // Clear URES IRQ
}

void ISR_Susp(void) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
	num++;
		if( num== 16 )
			num=0;
  EZUSB_IRQ_CLEAR();
  EPIRQ = bmBIT4;
 // USBIRQ = bmBIT4;         // Clear URES IRQ


}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}