/******************************************************************************
**
**  COPYRIGHT (C) 2000 Intel Corporation
**
**	FILENAME			:	XsOstRegs.h
**  Reference FILENAME	:   xsost.h
**
**  PURPOSE:		Operating System Timer header       
**
**  LAST MODIFIED: 12/20/2000
******************************************************************************/
#ifndef __XS_OST_REGS_H_
#define __XS_OST_REGS_H_

/*
************************************************************************************
*                             Register Physical Addresses 
************************************************************************************
*/
#define OSMR0_IDX	0	
#define OSMR1_IDX	1	
#define OSMR2_IDX	2	
#define OSMR3_IDX	3	
#define OSCR_IDX	4	
#define OSSR_IDX	5	
#define OWER_IDX	6	
#define OIER_IDX	7	

#define OST_PHY_BASE_ADDR	(0x40A00000)
#define OST_OSMR0_ADDR		(OST_PHY_BASE_ADDR + 0x0)
#define OST_OSMR1_ADDR		(OST_PHY_BASE_ADDR + 0x4)
#define OST_OSMR2_ADDR		(OST_PHY_BASE_ADDR + 0x8)
#define OST_OSMR3_ADDR		(OST_PHY_BASE_ADDR + 0xC)
#define OST_OSCR_ADDR		(OST_PHY_BASE_ADDR + 0x10)
#define OST_OSSR_ADDR		(OST_PHY_BASE_ADDR + 0x14)
#define OST_OWER_ADDR		(OST_PHY_BASE_ADDR + 0x18)
#define OST_OIER_ADDR		(OST_PHY_BASE_ADDR + 0x1C)

#define OST_OSMR0			*(volatile unsigned int *)OST_OSMR0_ADDR
#define OST_OSMR1			*(volatile unsigned int *)OST_OSMR1_ADDR
#define OST_OSMR2			*(volatile unsigned int *)OST_OSMR2_ADDR
#define OST_OSMR3			*(volatile unsigned int *)OST_OSMR3_ADDR
#define OST_OSCR			*(volatile unsigned int *)OST_OSCR_ADDR
#define OST_OSSR			*(volatile unsigned int *)OST_OSSR_ADDR
#define OST_OWER			*(volatile unsigned int *)OST_OWER_ADDR
#define OST_OIER			*(volatile unsigned int *)OST_OIER_ADDR

/*
************************************************************************************
*                             Bits and Length Definitions 
************************************************************************************
*/
// Bits Definitions for IER Reg.
// Note: 
//      - XX_OFS means the bit offset 
//	    - XX_SZ means the field length

#define	OSSR_M0_OFS		(0)
#define	OSSR_M1_OFS		(1)
#define	OSSR_M2_OFS		(2)
#define	OSSR_M3_OFS		(3)

#define	OWER_WME_OFS	(0)

#define OIER_E0_OFS		(0)
#define OIER_E1_OFS		(1)
#define OIER_E2_OFS		(2)
#define OIER_E3_OFS		(3)

/*
*******************************************************************************
Crystal constants
*******************************************************************************
*/
#define TICKS_PER_10_MSECS  36864   // number of ticks in 10 milliseconds

/*
*******************************************************************************
OS Timer Watchdog Match Enable Register (OWER)
*******************************************************************************
*/

#define OWER_WME    (0x1u << 0)     // Watchdog match enable

/*
*******************************************************************************
OS Timer Status Register (OSSR)
*******************************************************************************
*/

#define OSSR_M0     (0x1u << 0)     // Match status channel 0
#define OSSR_M1     (0x1u << 1)     // Match status channel 1
#define OSSR_M2     (0x1u << 2)     // Match status channel 2
#define OSSR_M3     (0x1u << 3)     // Match status channel 3

/*
*******************************************************************************
OS Timer Interrupt Enable Register (OIER)
*******************************************************************************
*/

#define OIER_E0     (0x1u << 0)     // Interrupt Enable Channel 0
#define OIER_E1     (0x1u << 1)     // Interrupt Enable Channel 1
#define OIER_E2     (0x1u << 2)     // Interrupt Enable Channel 2
#define OIER_E3     (0x1u << 3)     // Interrupt Enable Channel 3

/*
*******************************************************************************
OS Timer Registers 
*******************************************************************************
*/

typedef struct OSTRegsS
{
    unsigned int OSMR0;      // OS Timer Match Register 0
    unsigned int OSMR1;      // OS Timer Match Register 1
    unsigned int OSMR2;      // OS Timer Match Register 2
    unsigned int OSMR3;      // OS Timer Match Register 3
    unsigned int OSCR;       // OS Timer counter register
    unsigned int OSSR;       // OS Timer status register
    unsigned int OWER;       // OS Timer Watchdog enable register
    unsigned int OIER;       // OS Timer interrupt enable register
}OSTRegsT;

#define OST_REGISTER_BASE   0x40A00000

/*
*******************************************************************************
*    Test Constants
*******************************************************************************
*/
#define TEST_INTERVAL 1
#define TEST_EXTRA_INTERVAL 10
#define TEST_EXTRA_COUNT 4
#define TEST_TIMEBASE 3686


#endif //__XS_OST_REGS_H_