/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       XsIntCtrlRegs.h
**
**  PURPOSE:        register definition for the interrupt controller

**
**  EAS VERSION  :  2.1
**
**  $Modtime: 4/06/01 3:23p $ 
******************************************************************************/
#ifndef __XSINTCTRL_REGS_H
#define __XSINTCTRL_REGS_H

/*
************************************************************************************
*                             Register Physical Addresses 
************************************************************************************
*/
#define ICIP_IDX	0	
#define ICMR_IDX	1
#define ICLR_IDX	2	
#define ICFP_IDX	3	
#define ICPR_IDX	4	
#define ICCR_IDX	5	

#define INTREG_PHY_BASE_ADDR	(0x40D00000)	// FFUART Base Register Location
#define INT_ICIP_ADDR	(INTREG_PHY_BASE_ADDR+0x0)
#define INT_ICMP_ADDR	(INTREG_PHY_BASE_ADDR+0x4)
#define INT_ICLR_ADDR	(INTREG_PHY_BASE_ADDR+0x8)
#define INT_ICFP_ADDR	(INTREG_PHY_BASE_ADDR+0xC)
#define INT_ICPR_ADDR	(INTREG_PHY_BASE_ADDR+0x10)
#define INT_ICCR_ADDR	(INTREG_PHY_BASE_ADDR+0x14)

#define INT_ICIP		*(volatile unsigned int *)INT_ICIP_ADDR
#define INT_ICMR		*(volatile unsigned int *)INT_ICMP_ADDR
#define INT_ICLR		*(volatile unsigned int *)INT_ICLR_ADDR
#define INT_ICFP		*(volatile unsigned int *)INT_ICFP_ADDR
#define INT_ICPR		*(volatile unsigned int *)INT_ICPR_ADDR
#define INT_ICCR		*(volatile unsigned int *)INT_ICCR_ADDR

/*
************************************************************************************
*                             Bits and Length Definitions 
************************************************************************************
*/
// Bits Definitions for IER Reg.
// Note: 
//      - XX_OFS means the bit offset 
//	    - XX_SZ means the field length



    // Virtual memory address of first interrupt controller register.  
    //  System architecture has virtual addresses the same as the 
    //  physical addresses for I/O space.
#define XS_INTERRUPT_CONTROLLER_REG_BASE    0x40D00000

typedef struct XsIntCtrlRegsS
{                       // Interrupt Controller Reg usage

    unsigned int ICIP ;      // IRQ pending register 
    unsigned int ICMR ;      // Mask register  (set (1) bit enables interrupt)
    unsigned int ICLR ;      // Level register (select 0 = IRQ or 1 = FIQ)
    unsigned int ICFP ;      // FIQ Pending register
    unsigned int ICPR ;      // Pending register (all, whether or not enabled)
    unsigned int ICCR ;      // Control register (wakeup usage)

}  XsIntCtrlRegsT ;

#endif // #ifndef __XSINTCTRL_REGS_H