?? xsgpioregs.h
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/******************************************************************************
**
** COPYRIGHT (C) 2000 Intel Corporation
**
** FILENAME : XsGpioRegs.h
** Reference FILENAME : XsGpio.h/XsGpioApi.h
**
** PURPOSE: This file containes the GPIO's register definitions
**
** LAST MODIFIED: 12/20/2000
******************************************************************************/
#ifndef __xsgpioregs_h
#define __xsgpioregs_h
/*
************************************************************************************
* Included headers
************************************************************************************
*/
/*
************************************************************************************
* Register Physical Addresses
************************************************************************************
*/
#define GPIOREG_PHY_BASE_ADDR 0x40E00000
#define GPIO_GPLR0_ADDR (GPIOREG_PHY_BASE_ADDR+0x0) // GPLR_x, _y, _z: pin-level
#define GPIO_GPLR1_ADDR (GPIOREG_PHY_BASE_ADDR+0x4)
#define GPIO_GPLR2_ADDR (GPIOREG_PHY_BASE_ADDR+0x8)
#define GPIO_GPDR0_ADDR (GPIOREG_PHY_BASE_ADDR+0xC) // GPDR_x, _y, _z: pin direction
#define GPIO_GPDR1_ADDR (GPIOREG_PHY_BASE_ADDR+0x10)
#define GPIO_GPDR2_ADDR (GPIOREG_PHY_BASE_ADDR+0x14)
#define GPIO_GPSR0_ADDR (GPIOREG_PHY_BASE_ADDR+0x18) // GPSR_x, _y, _z: pin output set
#define GPIO_GPSR1_ADDR (GPIOREG_PHY_BASE_ADDR+0x1C)
#define GPIO_GPSR2_ADDR (GPIOREG_PHY_BASE_ADDR+0x20)
#define GPIO_GPCR0_ADDR (GPIOREG_PHY_BASE_ADDR+0x24) // GPCR_x, _y, _z: pin output clear
#define GPIO_GPCR1_ADDR (GPIOREG_PHY_BASE_ADDR+0x28)
#define GPIO_GPCR2_ADDR (GPIOREG_PHY_BASE_ADDR+0x2C)
#define GPIO_GRER0_ADDR (GPIOREG_PHY_BASE_ADDR+0x30) // GRER_x, _y, _z: rising-edge detect
#define GPIO_GRER1_ADDR (GPIOREG_PHY_BASE_ADDR+0x34)
#define GPIO_GRER2_ADDR (GPIOREG_PHY_BASE_ADDR+0x38)
#define GPIO_GFER0_ADDR (GPIOREG_PHY_BASE_ADDR+0x3C) // GFER_x, _y, _z: falling-edge detect
#define GPIO_GFER1_ADDR (GPIOREG_PHY_BASE_ADDR+0x40)
#define GPIO_GFER2_ADDR (GPIOREG_PHY_BASE_ADDR+0x44)
#define GPIO_GEDR0_ADDR (GPIOREG_PHY_BASE_ADDR+0x48) // GEDR_x, _y, _z: edge detect status
#define GPIO_GEDR1_ADDR (GPIOREG_PHY_BASE_ADDR+0x4C)
#define GPIO_GEDR2_ADDR (GPIOREG_PHY_BASE_ADDR+0x50)
#define GPIO_GAFR0_L_ADDR (GPIOREG_PHY_BASE_ADDR+0x54) // GAFR[0,1]_x, _y, _z: alternate function select
#define GPIO_GAFR0_U_ADDR (GPIOREG_PHY_BASE_ADDR+0x58)
#define GPIO_GAFR1_L_ADDR (GPIOREG_PHY_BASE_ADDR+0x5C)
#define GPIO_GAFR1_U_ADDR (GPIOREG_PHY_BASE_ADDR+0x60)
#define GPIO_GAFR2_L_ADDR (GPIOREG_PHY_BASE_ADDR+0x64)
#define GPIO_GAFR2_U_ADDR (GPIOREG_PHY_BASE_ADDR+0x68)
#define GPIO_GPLR0 *(volatile unsigned int *)GPIO_GPLR0_ADDR // GPLR_x, _y, _z: pin-level
#define GPIO_GPLR1 *(volatile unsigned int *)GPIO_GPLR1_ADDR
#define GPIO_GPLR2 *(volatile unsigned int *)GPIO_GPLR2_ADDR
#define GPIO_GPDR0 *(volatile unsigned int *)GPIO_GPDR0_ADDR // GPDR_x, _y, _z: pin direction
#define GPIO_GPDR1 *(volatile unsigned int *)GPIO_GPDR1_ADDR
#define GPIO_GPDR2 *(volatile unsigned int *)GPIO_GPDR2_ADDR
#define GPIO_GPSR0 *(volatile unsigned int *)GPIO_GPSR0_ADDR // GPSR_x, _y, _z: pin output set
#define GPIO_GPSR1 *(volatile unsigned int *)GPIO_GPSR1_ADDR
#define GPIO_GPSR2 *(volatile unsigned int *)GPIO_GPSR2_ADDR
#define GPIO_GPCR0 *(volatile unsigned int *)GPIO_GPCR0_ADDR // GPCR_x, _y, _z: pin output clear
#define GPIO_GPCR1 *(volatile unsigned int *)GPIO_GPCR1_ADDR
#define GPIO_GPCR2 *(volatile unsigned int *)GPIO_GPCR2_ADDR
#define GPIO_GRER0 *(volatile unsigned int *)GPIO_GRER0_ADDR // GRER_x, _y, _z: rising-edge detect
#define GPIO_GRER1 *(volatile unsigned int *)GPIO_GRER1_ADDR
#define GPIO_GRER2 *(volatile unsigned int *)GPIO_GRER2_ADDR
#define GPIO_GFER0 *(volatile unsigned int *)GPIO_GFER0_ADDR // GFER_x, _y, _z: falling-edge detect
#define GPIO_GFER1 *(volatile unsigned int *)GPIO_GFER1_ADDR
#define GPIO_GFER2 *(volatile unsigned int *)GPIO_GFER2_ADDR
#define GPIO_GEDR0 *(volatile unsigned int *)GPIO_GEDR0_ADDR // GEDR_x, _y, _z: edge detect status
#define GPIO_GEDR1 *(volatile unsigned int *)GPIO_GEDR1_ADDR
#define GPIO_GEDR2 *(volatile unsigned int *)GPIO_GEDR2_ADDR
#define GPIO_GAFR0_L *(volatile unsigned int *)GPIO_GAFR0_L_ADDR // GAFR[0,1]_x, _y, _z: alternate function select
#define GPIO_GAFR0_U *(volatile unsigned int *)GPIO_GAFR0_U_ADDR
#define GPIO_GAFR1_L *(volatile unsigned int *)GPIO_GAFR1_L_ADDR
#define GPIO_GAFR1_U *(volatile unsigned int *)GPIO_GAFR1_U_ADDR
#define GPIO_GAFR2_L *(volatile unsigned int *)GPIO_GAFR2_L_ADDR
#define GPIO_GAFR2_U *(volatile unsigned int *)GPIO_GAFR2_U_ADDR
//register group definitions
#define GPIO_GROUP0 0 //group 0 select GPIO_GXXR0, or GPIO_GAFR0_L
#define GPIO_GROUP1 1 //group 1 select GPIO_GXXR1, or GPIO_GAFR0_U
#define GPIO_GROUP2 2 //group 2 select GPIO_GXXR2, or GPIO_GAFR1_L
#define GPIO_GROUP3 3 //group 3 select GPIO_GAFR1_U
#define GPIO_GROUP4 4 //group 4 select GPIO_GAFR2_L
#define GPIO_GROUP5 5 //group 5 select GPIO_GAFR1_U
#define GPIO_GPLR_ADDR(group) (GPIO_GPLR0_ADDR + group * 4) // GPLR_x, _y, _z: pin-level
#define GPIO_GPDR_ADDR(group) (GPIO_GPDR0_ADDR + group * 4) // GPDR_x, _y, _z: pin direction
#define GPIO_GPSR_ADDR(group) (GPIO_GPSR0_ADDR + group * 4) // GPSR_x, _y, _z: pin output set
#define GPIO_GPCR_ADDR(group) (GPIO_GPCR0_ADDR + group * 4) // GPCR_x, _y, _z: pin output clear
#define GPIO_GRER_ADDR(group) (GPIO_GRER0_ADDR + group * 4) // GRER_x, _y, _z: rising-edge detect
#define GPIO_GFER_ADDR(group) (GPIO_GFER0_ADDR + group * 4) // GFER_x, _y, _z: falling-edge detect
#define GPIO_GEDR_ADDR(group) (GPIO_GEDR0_ADDR + group * 4) // GEDR_x, _y, _z: edge detect status
#define GPIO_GAFR_ADDR(group) (GPIO_GAFR0_L_ADDR + group * 4) // GAFR[0,1]_x, _y, _z: alternate function select
//#define GPIO_GAFR_U_ADDR(group) (GPIO_GAFR0_U_ADDR + group * 4)
#define GPIO_GPLR(group) *(volatile unsigned int *)(GPIO_GPLR_ADDR(group)) // GPLR_x, _y, _z: pin-level
#define GPIO_GPDR(group) *(volatile unsigned int *)(GPIO_GPDR_ADDR(group)) // GPDR_x, _y, _z: pin direction
#define GPIO_GPSR(group) *(volatile unsigned int *)(GPIO_GPSR_ADDR(group)) // GPSR_x, _y, _z: pin output set
#define GPIO_GPCR(group) *(volatile unsigned int *)(GPIO_GPCR_ADDR(group)) // GPCR_x, _y, _z: pin output clear
#define GPIO_GRER(group) *(volatile unsigned int *)(GPIO_GRER_ADDR(group)) // GRER_x, _y, _z: rising-edge detect
#define GPIO_GFER(group) *(volatile unsigned int *)(GPIO_GFER_ADDR(group)) // GFER_x, _y, _z: falling-edge detect
#define GPIO_GEDR(group) *(volatile unsigned int *)(GPIO_GEDR_ADDR(group)) // GEDR_x, _y, _z: edge detect status
#define GPIO_GAFR(group) *(volatile unsigned int *)(GPIO_GAFR_ADDR(group)) // GAFR[0,1]_x, _y, _z: alternate function select
//#define GPIO_GAFR_U(group) *(volatile unsigned int *)(GPIO_GAFR_U_ADDR(group))
/*
************************************************************************************
* Bit Offset and Length Definition
************************************************************************************
*/
#define GXXR_GPIO0_OFS 0 // GPIO_GXXR0
#define GXXR_GPIO1_OFS 1
#define GXXR_GPIO2_OFS 2
#define GXXR_GPIO3_OFS 3
#define GXXR_GPIO4_OFS 4
#define GXXR_GPIO5_OFS 5
#define GXXR_GPIO6_OFS 6
#define GXXR_GPIO7_OFS 7
#define GXXR_GPIO8_OFS 8
#define GXXR_GPIO9_OFS 9
#define GXXR_GPIO10_OFS 10
#define GXXR_GPIO11_OFS 11
#define GXXR_GPIO12_OFS 12
#define GXXR_GPIO13_OFS 13
#define GXXR_GPIO14_OFS 14
#define GXXR_GPIO15_OFS 15
#define GXXR_GPIO16_OFS 16
#define GXXR_GPIO17_OFS 17
#define GXXR_GPIO18_OFS 18
#define GXXR_GPIO19_OFS 19
#define GXXR_GPIO20_OFS 20
#define GXXR_GPIO21_OFS 21
#define GXXR_GPIO22_OFS 22
#define GXXR_GPIO23_OFS 23
#define GXXR_GPIO24_OFS 24
#define GXXR_GPIO25_OFS 25
#define GXXR_GPIO26_OFS 26
#define GXXR_GPIO27_OFS 27
#define GXXR_GPIO28_OFS 28
#define GXXR_GPIO29_OFS 29
#define GXXR_GPIO30_OFS 30
#define GXXR_GPIO31_OFS 31
#define GXXR_GPIO32_OFS 0 // GPIO_GXXR1
#define GXXR_GPIO33_OFS 1
#define GXXR_GPIO34_OFS 2
#define GXXR_GPIO35_OFS 3
#define GXXR_GPIO36_OFS 4
#define GXXR_GPIO37_OFS 5
#define GXXR_GPIO38_OFS 6
#define GXXR_GPIO39_OFS 7
#define GXXR_GPIO40_OFS 8
#define GXXR_GPIO41_OFS 9
#define GXXR_GPIO42_OFS 10
#define GXXR_GPIO43_OFS 11
#define GXXR_GPIO44_OFS 12
#define GXXR_GPIO45_OFS 13
#define GXXR_GPIO46_OFS 14
#define GXXR_GPIO47_OFS 15
#define GXXR_GPIO48_OFS 16
#define GXXR_GPIO49_OFS 17
#define GXXR_GPIO50_OFS 18
#define GXXR_GPIO51_OFS 19
#define GXXR_GPIO52_OFS 20
#define GXXR_GPIO53_OFS 21
#define GXXR_GPIO54_OFS 22
#define GXXR_GPIO55_OFS 23
#define GXXR_GPIO56_OFS 24
#define GXXR_GPIO57_OFS 25
#define GXXR_GPIO58_OFS 26
#define GXXR_GPIO59_OFS 27
#define GXXR_GPIO60_OFS 28
#define GXXR_GPIO61_OFS 29
#define GXXR_GPIO62_OFS 30
#define GXXR_GPIO63_OFS 31
#define GXXR_GPIO64_OFS 0 // GPIO_GXXR2
#define GXXR_GPIO65_OFS 1
#define GXXR_GPIO66_OFS 2
#define GXXR_GPIO67_OFS 3
#define GXXR_GPIO68_OFS 4
#define GXXR_GPIO69_OFS 5
#define GXXR_GPIO70_OFS 6
#define GXXR_GPIO71_OFS 7
#define GXXR_GPIO72_OFS 8
#define GXXR_GPIO73_OFS 9
#define GXXR_GPIO74_OFS 10
#define GXXR_GPIO75_OFS 11
#define GXXR_GPIO76_OFS 12
#define GXXR_GPIO77_OFS 13
#define GXXR_GPIO78_OFS 14
#define GXXR_GPIO79_OFS 15
#define GXXR_GPIO80_OFS 16
#define GAFR_AF0_OFS 0 // GAFR0_L
#define GAFR_AF1_OFS 2
#define GAFR_AF2_OFS 4
#define GAFR_AF3_OFS 6
#define GAFR_AF4_OFS 8
#define GAFR_AF5_OFS 10
#define GAFR_AF6_OFS 12
#define GAFR_AF7_OFS 14
#define GAFR_AF8_OFS 16
#define GAFR_AF9_OFS 18
#define GAFR_AF10_OFS 20
#define GAFR_AF11_OFS 22
#define GAFR_AF12_OFS 24
#define GAFR_AF13_OFS 26
#define GAFR_AF14_OFS 28
#define GAFR_AF15_OFS 30
#define GAFR_AF16_OFS 0 // GAFR0_U
#define GAFR_AF17_OFS 2
#define GAFR_AF18_OFS 4
#define GAFR_AF19_OFS 6
#define GAFR_AF20_OFS 8
#define GAFR_AF21_OFS 10
#define GAFR_AF22_OFS 12
#define GAFR_AF23_OFS 14
#define GAFR_AF24_OFS 16
#define GAFR_AF25_OFS 18
#define GAFR_AF26_OFS 20
#define GAFR_AF27_OFS 22
#define GAFR_AF28_OFS 24
#define GAFR_AF29_OFS 26
#define GAFR_AF30_OFS 28
#define GAFR_AF31_OFS 30
#define GAFR_AF32_OFS 0 // GAFR1_L
#define GAFR_AF33_OFS 2
#define GAFR_AF34_OFS 4
#define GAFR_AF35_OFS 6
#define GAFR_AF36_OFS 8
#define GAFR_AF37_OFS 10
#define GAFR_AF38_OFS 12
#define GAFR_AF39_OFS 14
#define GAFR_AF40_OFS 16
#define GAFR_AF41_OFS 18
#define GAFR_AF42_OFS 20
#define GAFR_AF43_OFS 22
#define GAFR_AF44_OFS 24
#define GAFR_AF45_OFS 26
#define GAFR_AF46_OFS 28
#define GAFR_AF47_OFS 30
#define GAFR_AF48_OFS 0 // GAFR1_U
#define GAFR_AF49_OFS 2
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