/******************************************************************************
**
**  COPYRIGHT (C) 2000 Intel Corporation
**
**	FILENAME			:	XsClkMgrRegs.h
**  Reference FILENAME	:   xsClkMgr.h
**
**  PURPOSE:		This file containes the UART's register definitions		       
**
**  LAST MODIFIED: 12/20/2000
******************************************************************************/

#ifndef __XSCLKMGR_REGS_H
#define __XSCLKMGR_REGS_H

/*
************************************************************************************
*                             Register Physical Addresses 
************************************************************************************
*/
#define CCCR_IDX	0	
#define CKEN_IDX	1
#define OSCC_IDX	2

#define CLKMGRREG_PHY_BASE_ADDR	(0x41300000)	// Clk Manager Base Register Location
#define CLKMGR_CCCR_ADDR	(CLKMGRREG_PHY_BASE_ADDR + 0x0)
#define CLKMGR_CKEN_ADDR	(CLKMGRREG_PHY_BASE_ADDR + 0x4)
#define CLKMGR_OSCC_ADDR	(CLKMGRREG_PHY_BASE_ADDR + 0x8)

#define CLKMGR_CCCR	*(volatile unsigned int *)CLKMGR_CCCR_ADDR
#define CLKMGR_CKEN	*(volatile unsigned int *)CLKMGR_CKEN_ADDR
#define CLKMGR_OSCC	*(volatile unsigned int *)CLKMGR_OSCC_ADDR

/*
************************************************************************************
*                             Bits and Length Definitions 
************************************************************************************
*/
// Note: 
//      - XX_OFS means the bit offset 
//	    - XX_SZ means the field length

#define	CCCR_L_OFS	(0)
#define	CCCR_L_SZ	(5)
#define	CCCR_M_OFS	(5)
#define	CCCR_M_SZ	(2)
#define	CCCR_N_OFS	(7)
#define	CCCR_N_SZ	(3)

#define CKEN_CK_PWM0_OFS	(0)
#define CKEN_CK_PWM1_OFS	(1)
#define CKEN_CK_AC97_OFS	(2)
#define CKEN_CK_SSP_OFS		(3)
#define CKEN_RSV4_OFS		(4)
#define CKEN_CK_STUART_OFS	(5)
#define CKEN_CK_FFUART_OFS	(6)
#define CKEN_CK_BTUART_OFS	(7)
#define CKEN_CK_I2S_OFS		(8)
#define CKEN_RSV9_OFS		(9)
#define CKEN_RSV10_OFS		(10)	//CK_ADC not exist in PXA250
#define CKEN_CK_USB_OFS		(11)	
#define CKEN_CK_MMC_OFS		(12)
#define CKEN_CK_ICP_OFS		(13)
#define CKEN_CK_I2C_OFS		(14)
#define CKEN_RSV15_OFS		(15)
#define CKEN_CK_LCD_OFS		(16)
    
#define OSCC_OOK_OFS	(0)
#define OSCC_OON_OFS	(1)
/*
*******************************************************************************
The clock enable register CKEN.
The naming of these bits conforms to the standard whereby the action 
is specified in the name when the bit is set. However, these bits will be 
used for both enabling and disabling the clocks. Therefore an alias is created 
for each of these bits. The alias is the next section.
*******************************************************************************
*/
#define PWM0_CE     (0x1u << 0)     // PWM #0 clock enable
#define PWM1_CE     (0x1u << 1)     // PWM #1 clock enable
#define AC97_CE     (0x1u << 2)     // AC97 
#define SSP_CE      (0x1u << 3)     // SSP
#define STUART_CE   (0x1u << 5)     // Standard UART
#define FFUART_CE   (0x1u << 6)     // Full Function UART
#define BTUART_CE   (0x1u << 7)     // Bluetooth UART
#define I2S_CE      (0x1u << 9)     // I2S
#define ADC_CE      (0x1u << 10)    // ADC 
#define USB_CE      (0x1u << 11)    // USB
#define MMC_CE      (0x1u << 12)    // MMC
#define ICP_CE      (0x1u << 13)    // ICP
#define I2C_CE      (0x1u << 14)    // I2C
#define LCD_CE      (0x1u << 16)    // LCD 

/*
*******************************************************************************
Aliases for the device clock enables. The enable and disable procedure takes
a single UINT32 as a parameter. This UINT32 contains the bit settings for the 
devices that are being enabled or disabled.
*******************************************************************************
*/

typedef enum periphClkNamesS
{

    CK_PWM0   =  PWM0_CE,
    CK_PWM1   =  PWM1_CE,  
    CK_AC97   =  AC97_CE,  
    CK_SSP    =  SSP_CE,   
    CK_STUART =  STUART_CE,
    CK_FFUART =  FFUART_CE,
    CK_BTUART =  BTUART_CE,
    CK_I2S    =  I2S_CE,   
    CK_ADC    =  ADC_CE,   
    CK_USB    =  USB_CE,   
    CK_MMC    =  MMC_CE,   
    CK_ICP    =  ICP_CE,   
    CK_I2C    =  I2C_CE,   
    CK_LCD    =  LCD_CE
} periphClkNamesT;   

/*
*******************************************************************************
Note: The following structure defines all of the Clock manager registers, 
but only the CKEN register is manipulated in this module. The other registers
should have been pre-programmed by the assembly language startup code.
*******************************************************************************
*/
#define CKEN_REGISTER_BASE      0x41300000

typedef struct clkMgrRegsS
{
    unsigned int CCCR;       // Core clock configuration register
    unsigned int CKEN;       // Clock Enable register
    unsigned int OSCC;       // Oscillator Configuration register
}clkMgrRegsT;

#endif //__XSCLKMGR_REGS_H