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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch05.css"><TITLE> 5.1 Execution of a model</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="ch05.htm">Chapter start</A> <A HREF="ch05.htm">Previous page</A> <A HREF="ch05.2.htm">Next page</A></P></DIV><H1 CLASS="Section"><A NAME="pgfId=84"> </A>5.1 Execution of a model</H1><P CLASS="Body"><A NAME="pgfId=85"> </A>The balance of the sections of this specification describe the behavior of each of the elements of the language. This section gives an overview of the interactions between these elements, especially with respect to the scheduling and execution of events.</P><P CLASS="Body"><A NAME="pgfId=102"> </A>Verilog is a hardware description language (HDL). The elements of the language can be used to describe the behavior, at varying levels of abstraction, of electronic hardware. A hardware description language must be a parallel programming language. The execution of certain language constructs is defined by parallel execution of blocks or processes. It is important to understand what execution order is guaranteed to the user, and what execution order is indeterminate.</P><P CLASS="Body"><A NAME="pgfId=103"> </A>Although Verilog HDL is used for more than simulation, the semantics of the language are defined for simulation, and everything else is abstracted from this base definition.</P><HR><P><A HREF="ch05.htm">Chapter start</A> <A HREF="ch05.htm">Previous page</A> <A HREF="ch05.2.htm">Next page</A></P></BODY></HTML>?? 快捷鍵說明
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