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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"><HTML><HEAD><META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"><LINK REL="STYLESHEET" HREF="ch17.css"><TITLE> Section 17</TITLE></HEAD><BODY BGCOLOR="#ffffff"><DIV><HR><P><A HREF="none">Chapter start</A> <A HREF="none">Next page</A></P></DIV><DIV><H2 CLASS="SectionNum"><A NAME="pgfId=255"> </A><A NAME="27886"> </A></H2></DIV><DIV><H2 CLASS="SectionTitle"><A NAME="pgfId=138"> </A><A NAME="marker=24"> </A>PLI TF and ACC interface mechanism</H2><P CLASS="BodyText"><A NAME="pgfId=139"> </A>The interface mechanism described in this section provides a means for users to link applications based on PLI task/function (TF) routines and access (ACC) routines to Verilog software products. Through the interface mechanism, a user will:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=144"> </A>Specify a <A NAME="marker=38"> </A>user-defined <A NAME="marker=44"> </A>system <A NAME="marker=45"> </A>task or function <A NAME="marker=51"> </A>name that may be included in Verilog HDL source descriptions; the user-defined system task or function name must begin with a dollar sign (<A NAME="marker=54"> </A>$), such as <EM CLASS="Italic">$get_vector</EM> </LI><LI CLASS="DashedList"><A NAME="pgfId=140"> </A>Provide one or more PLI C applications to be called by a software implementation (such as a logic simulator)</LI><LI CLASS="DashedList"><A NAME="pgfId=155"> </A>Define which PLI C applications are to be called--and when the applications should be called--when the user-defined system task or function name is encountered in the Verilog HDL source description</LI><LI CLASS="DashedList"><A NAME="pgfId=171"> </A>Define whether the PLI C applications should be treated as <EM CLASS="Italic">function</EM>s (which return a value), or <EM CLASS="Italic">task</EM>s (analogous to subroutines in other programming languages)</LI><LI CLASS="DashedList"><A NAME="pgfId=245"> </A>Define a data argument to be passed to the PLI C routines each time they are called</LI></UL><P CLASS="Note"><A NAME="pgfId=243"> </A>Note: The PLI interface mechanism described in this section may not apply to applications which use the Verilog Procedural Interface (VPI) routines; these routines use the VPI registry mechanism described in <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/ch22.htm#42361" CLASS="XRef"></A> and <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/ch23.htm#19452" CLASS="XRef"></A>.</P><DIV><H3 CLASS="H2(1.1)"><A NAME="pgfId=157"> </A>PLI purpose and <A NAME="marker=135"> </A>history</H3><P CLASS="BodyText"><A NAME="pgfId=159"> </A><A HREF="ch17.htm#27886" CLASS="XRef">See </A> through <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/ch23.htm#19452" CLASS="XRef"></A> and <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/annG.htm#74208" CLASS="XRef"></A> through <A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/annE.htm#50345" CLASS="XRef"></A> describe the C-language procedural interface standard and interface mechanisms which are part of the Verilog Hardware Description Language. This procedural interface, known as the Programming Language Interface, or PLI, provides a means for Verilog HDL users to dynamically access and modify data in an instantiated Verilog HDL data structure. An instantiated Verilog HDL data structure is the result of compiling Verilog HDL source descriptions and generating the hierarchy modeled by module instances, primitive instances, and other Verilog HDL constructs which represent scope. The PLI procedural interface provides a library of C language functions which can directly access data within an instantiated Verilog HDL data structure.</P><P CLASS="BodyText"><A NAME="pgfId=211"> </A>A few of the many possible applications for the PLI procedural interface are:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=220"> </A>C language delay calculators for Verilog model libraries that can dynamically scan the data structure of a Verilog simulation or timing analyzer and then dynamically modify the delays of each instance of models from the library</LI><LI CLASS="DashedList"><A NAME="pgfId=225"> </A>C language routines that dynamically read test vectors or other data from a file and pass the data into a Verilog logic simulator or fault simulator </LI><LI CLASS="DashedList"><A NAME="pgfId=226"> </A>Custom graphical waveform and debugging environments for Verilog simulators</LI><LI CLASS="DashedList"><A NAME="pgfId=252"> </A>Source code decompilers that can generate Verilog HDL source code from the compiled data structure of a Verilog software product</LI><LI CLASS="DashedList"><A NAME="pgfId=253"> </A>Simulation models written in the C language and dynamically linked into Verilog HDL simulations</LI><LI CLASS="DashedList"><A NAME="pgfId=254"> </A>Interfaces to actual hardware, such as a hardware modeler, that dynamically interact with simulations</LI></UL><P CLASS="BodyText"><A NAME="pgfId=257"> </A>The IEEE-1364 Verilog PLI is a standardization of a public domain Verilog PLI that has been in use since the mid 1980's. The 1364 standard comprises three primary generations of public domain PLI routines.</P><OL><P CLASS="NumberedLista"><A NAME="pgfId=268"> </A>a) <A NAME="marker=107"> </A><EM CLASS="Italic">Task/function</EM> routines, called <EM CLASS="ItalicBold">TF</EM> routines, make up the first generation of the PLI. These routines, most of which start with the characters <EM CLASS="ItalicBold">tf_</EM>, are primarily used for operations involving user-defined task/function arguments, along with utility functions such as setting up call-back mechanisms, and writing data to output devices. The TF routines are sometimes referred to as "utility routines"</P><P CLASS="NumberedListb"><A NAME="pgfId=269"> </A>b) <EM CLASS="Italic">Access</EM><A NAME="marker=117"> </A> routines, called <EM CLASS="ItalicBold">ACC</EM> routines, form the second generation of the PLI. These routines, which all start with the characters <EM CLASS="ItalicBold">acc_</EM>, provide an object oriented access directly into a Verilog HDL structural description. ACC routines are used to access and modify information, such as delay values and logic values on a wide variety of objects that exist in a Verilog HDL description. There is some overlap in functionality between ACC routines and TF routines.</P><P CLASS="NumberedListb"><A NAME="pgfId=270"> </A>c) <A NAME="marker=118"> </A>Verilog Procedural Interface routines, called <EM CLASS="ItalicBold">VPI</EM> routines, are the third generation of the PLI. These routines, all of which start with the characters <EM CLASS="ItalicBold">vpi_</EM>, provide an object oriented access for both Verilog HDL structural and behavioral objects. The VPI routines are a superset of the functionality of the TF routines and ACC routines.</P></OL><P CLASS="BodyText"><A NAME="pgfId=271"> </A>The first two generations of PLI routines were first developed as part of a proprietary commercial digital logic simulator product, and were released to the public domain in 1990. After release to the public domain, the TF routines and ACC routines became known as the <A NAME="marker=119"> </A>Open Verilog International (<A NAME="marker=120"> </A>OVI) <A NAME="marker=121"> </A>PLI 1.0 standard. The OVI PLI 1.0 standard did not document a number of TF and ACC routines that were widely used in commercial Verilog HDL software products. The IEEE-1364 Verilog PLI standard includes both the public domain OVI PLI 1.0 routines and the de facto standard PLI routines in use in commercial products.</P><P CLASS="BodyText"><A NAME="pgfId=272"> </A>The third generation PLI routines, the VPI routines, were first introduced in 1993 by OVI under the title of <A NAME="marker=122"> </A>PLI 2.0. OVI intended PLI 2.0 to replace PLI 1.0--the VPI routines provide more functionality with simpler syntax and semantics than the TF and ACC routines. However, this approach did not provide adequate backward compatibility with existing PLI applications. Therefore, the IEEE-1364 Verilog PLI standard includes all three generations of the PLI routines.</P></DIV><DIV><H3 CLASS="H2(1.1)"><A NAME="pgfId=137"> </A>User-defined task or function names</H3><P CLASS="BodyText"><A NAME="pgfId=247"> </A>A user-defined task or function name is the name which will be used within a Verilog HDL source file to invoke specific PLI C routines. The name must adhere to the following rules:</P><UL><LI CLASS="DashedList"><A NAME="pgfId=249"> </A>The first character of the name must be the dollar sign character ( $ )</LI><LI CLASS="DashedList"><A NAME="pgfId=251"> </A>The remaining characters may be letters, digits, the underscore character ( _ ), or the dollar character ( $ )</LI><LI CLASS="DashedList"><A NAME="pgfId=273"> </A>Upper and lower case letters are considered to be unique--the name is case sensitive</LI><LI CLASS="DashedList"><A NAME="pgfId=274"> </A>The name may be any size, and all characters are significant</LI></UL></DIV><DIV><H3 CLASS="H2(1.1)"><A NAME="pgfId=248"> </A><A NAME="marker=55"> </A>Overloading built-in system task and function names</H3><P CLASS="BodyText"><A NAME="pgfId=275"> </A><A HREF="/Humuhumu/Files/Prof_Smith/Academic/ASICs/Web/ASICs/HTML/Verilog/LRM/HTML/17/ch14.htm#21043" CLASS="XRef"></A> of this document defines a number of built-in system tasks and functions which are part of the Verilog language. In addition, software implementations may include other built-in system tasks and functions specific to the implementation. These built-in system tasks and functions also begin with the dollar sign character ( $ ).</P><P CLASS="BodyText"><A NAME="pgfId=250"> </A>Using the PLI interface mechanism, it is possible to overload the definition of a built-in system task or function by simply using the same name; for example, a user could write a random number generator as a PLI C routine, and then associate the PLI routine with the name <EM CLASS="Italic">$random</EM>, thereby overriding the built-in <EM CLASS="Italic">$random</EM> function with the PLI C routine.</P></DIV><DIV><H3 CLASS="H2(1.1)"><A NAME="pgfId=201"> </A>User supplied PLI C applications</H3><P CLASS="BodyText"><A NAME="pgfId=189"> </A>User supplied C applications are C language functions that utilize the library of PLI C functions to dynamically access and interact with Verilog HDL software implementations as the Verilog HDL source code is executed.</P><P CLASS="BodyText"><A NAME="pgfId=246"> </A>These PLI C applications are not independent C programs. They are C functions, which are linked into a software implementation, and become part of the implementation. This allows the PLI C application to be called when the user-defined system task or function $ name is compiled or executed in the Verilog HDL source code.</P><P CLASS="BodyText"><A NAME="pgfId=145"> </A>The PLI interface mechanism provides a means to have PLI C applications called for various reasons when the associated system task or function $ name is encountered in the Verilog HDL source description. For example, when a Verilog HDL simulator first compiles the Verilog HDL source description, a specific PLI C application may be called that performs syntax checking to ensure the user-defined system task or function is being used correctly. Then, as simulation is executing, a different PLI C application may be called to perform the operations required by the PLI application. Other PLI C application can be automatically called by the simulator for miscellaneous reasons, such as the end of a simulation time step or a logic value change on a specific signal.</P><P CLASS="BodyText"><A NAME="pgfId=186"> </A>The PLI interface mechanism for TF and ACC routines provides five classes of user supplied PLI C applications, <EM CLASS="ItalicBold">checktf</EM> routines, <EM CLASS="ItalicBold">sizetf</EM> routines, <EM CLASS="ItalicBold">calltf</EM> routines, <EM CLASS="ItalicBold">misctf</EM> routines and <EM CLASS="ItalicBold">consumer</EM> routines. The purpose of each of the PLI routine classes is explained in the following sections.</P><DIV><H4 CLASS="H3(1.1.1)"><A NAME="pgfId=281"> </A>The <A NAME="marker=60"> </A><EM CLASS="Italic">calltf</EM> class of PLI C routines</H4><P CLASS="BodyText"><A NAME="pgfId=285"> </A>A <EM CLASS="ItalicBold">calltf</EM> PLI routine is called each time the associated user defined system task or function is executed within the Verilog HDL source code. For example, the following Verilog loop would call the PLI <EM CLASS="ItalicBold">calltf</EM> routine that is associated with the <EM CLASS="Italic">$get_vector</EM> user-defined system task name 1024 times:</P><PRE CLASS="CodeIndent"><A NAME="pgfId=286"> </A>for (i = 1; i <= 1024; i = i + 1) </PRE><PRE CLASS="CodeIndent"><A NAME="pgfId=287"> </A> @(posedge clk) $get_vector("test_vector.pat", input_bus); </PRE><P CLASS="BodyText"><A NAME="pgfId=280"> </A>In this example, the user supplied PLI <EM CLASS="ItalicBold">calltf</EM> C routine might read a test vector from a file called <EM CLASS="Italic">test_vector.pat</EM> (the first task/function argument), perhaps manipulate the vector to put in a proper format for Verilog, and then assign the vector value to the second task/function argument called <EM CLASS="Italic">input_bus</EM>.</P></DIV><DIV><H4 CLASS="H3(1.1.1)"><A NAME="pgfId=277"> </A>The <A NAME="marker=59"> </A>c<EM CLASS="Italic">hecktf</EM> class of PLI C routines</H4><P CLASS="BodyText"><A NAME="pgfId=284"> </A>A <EM CLASS="ItalicBold">checktf</EM> PLI routine will be called when the user-defined system task or function name is encountered during parsing or compiling the Verilog HDL source code. This routine is typically used to check the correctness of any arguments used with the system task in the Verilog HDL source code. The <EM CLASS="ItalicBold">checktf</EM> PLI routine is called one time for each system task or function reference in the source description. Providing a <EM CLASS="ItalicBold">checktf</EM> routine is optional, but it is recommended that any arguments used with the system task or function be checked for correctness to avoid problems when the <EM CLASS="Italic">calltf</EM> or other PLI routines read and perform operations on the arguments. </P></DIV><DIV><H4 CLASS="H3(1.1.1)"><A NAME="pgfId=278"> </A>The <A NAME="marker=61"> </A><EM CLASS="Italic">sizetf</EM> class of PLI routines</H4><P CLASS="BodyText"><A NAME="pgfId=276"> </A>A <EM CLASS="ItalicBold">sizetf</EM> PLI routine is used in conjunction with user-defined system <EM CLASS="Italic">functions</EM>. A function will return a value, and the software implementations that execute the system function may need to determine how many bits wide that return will be. The user supplied PLI <EM CLASS="ItalicBold">sizetf</EM> routine is called one time by the software implementation, typically when the Verilog HDL source code is compiled; when called, the <EM CLASS="ItalicBold">sizetf</EM> routine must return the number of bits of the system function return value. The <EM CLASS="ItalicBold">sizetf</EM> routine is not called for PLI system tasks.</P></DIV><DIV><H4 CLASS="H3(1.1.1)"><A NAME="pgfId=279"> </A>The <A NAME="marker=62"> </A><EM CLASS="Italic">misctf</EM> class of PLI routines</H4><P CLASS="BodyText"><A NAME="pgfId=282"> </A>A <EM CLASS="ItalicBold">?? 快捷鍵說明
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