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<HTML><HEAD> <META NAME="GENERATOR" CONTENT="Adobe PageMill 2.0 Mac"> <LINK REL="STYLESHEET" HREF="ch04.css"> <TITLE> 4.1 Operators </TITLE></HEAD><BODY BGCOLOR="#ffffff"><P><A NAME="pgfId=539"></A><HR ALIGN=LEFT></P><P><A HREF="ch04.htm">Chapter start</A> <A HREF="ch04.htm">Previous page</A> <A HREF="ch04.2.htm">Next page</A></P><H1>4.1 Operators</H1><P><P CLASS="Body"><A NAME="pgfId=466"></A>The symbols for the Verilog HDLoperators are similar to those in the C programming language. Table 4-1lists these operators.</P><P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2"><CAPTION ALIGN="TOP"><P CLASS="TableTitle"><A NAME="pgfId=473"></A>Table 4-1: Operatorsin Verilog HDL</CAPTION><TR><TD><P CLASS="CellBody"><A NAME="pgfId=522"></A>{}, {{}}</TD><TD><P CLASS="CellBody"><A NAME="pgfId=540"></A>concatenation, replication</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=549"></A>+ - * /</TD><TD><P CLASS="CellBody"><A NAME="pgfId=551"></A>arithmetic</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=552"></A>%</TD><TD><P CLASS="CellBody"><A NAME="pgfId=583"></A>modulus</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=613"></A>> >= < <=</TD><TD><P CLASS="CellBody"><A NAME="pgfId=616"></A>relational</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=620"></A>!</TD><TD><P CLASS="CellBody"><A NAME="pgfId=736"></A>logical negation</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=737"></A>&&</TD><TD><P CLASS="CellBody"><A NAME="pgfId=738"></A>logical and</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=740"></A>||</TD><TD><P CLASS="CellBody"><A NAME="pgfId=741"></A>logical or</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=751"></A>==</TD><TD><P CLASS="CellBody"><A NAME="pgfId=756"></A>logical equality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=757"></A>!=</TD><TD><P CLASS="CellBody"><A NAME="pgfId=758"></A>logical inequality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=759"></A>===</TD><TD><P CLASS="CellBody"><A NAME="pgfId=760"></A>case equality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=761"></A>!==</TD><TD><P CLASS="CellBody"><A NAME="pgfId=762"></A>case inequality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=763"></A>~</TD><TD><P CLASS="CellBody"><A NAME="pgfId=773"></A>bit-wise negation</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=806"></A>&</TD><TD><P CLASS="CellBody"><A NAME="pgfId=810"></A>bit-wise and</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=811"></A>|</TD><TD><P CLASS="CellBody"><A NAME="pgfId=812"></A>bit-wise inclusive or</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=813"></A>^</TD><TD><P CLASS="CellBody"><A NAME="pgfId=814"></A>bit-wise exclusive or</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=815"></A>^~ or ~^</TD><TD><P CLASS="CellBody"><A NAME="pgfId=819"></A>bit-wise equivalence</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=820"></A>&</TD><TD><P CLASS="CellBody"><A NAME="pgfId=823"></A>reduction and</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=824"></A>~&</TD><TD><P CLASS="CellBody"><A NAME="pgfId=825"></A>reduction nand</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=838"></A>|</TD><TD><P CLASS="CellBody"><A NAME="pgfId=839"></A>reduction or</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=855"></A>~|</TD><TD><P CLASS="CellBody"><A NAME="pgfId=856"></A>reduction nor</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=857"></A>^</TD><TD><P CLASS="CellBody"><A NAME="pgfId=858"></A>reduction xor</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=859"></A>~^ or ^~</TD><TD><P CLASS="CellBody"><A NAME="pgfId=860"></A>reduction xnor</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=861"></A><<</TD><TD><P CLASS="CellBody"><A NAME="pgfId=863"></A>left shift</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=869"></A>>></TD><TD><P CLASS="CellBody"><A NAME="pgfId=871"></A>right shift</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=897"></A>? :</TD><TD><P CLASS="CellBody"><A NAME="pgfId=898"></A>conditional</TD></TR></TABLE><P CLASS="SubSection"><A NAME="pgfId=899"></A>Operators with real operands</P><P><P CLASS="Body"><A NAME="pgfId=931"></A>The operators shown in <A HREF="#pgfId=904">Table 4-2</A> shall be legal when applied to real operands.All other operators shall be considered illegal when used with real operands.</P><P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2"><CAPTION ALIGN="TOP"><P CLASS="TableTitle"><A NAME="pgfId=904"></A>Table 4-2: Legal operatorsfor use in real expressions</CAPTION><TR><TD><P CLASS="CellBody"><A NAME="pgfId=915"></A>unary + unary -</TD><TD><P CLASS="CellBody"><A NAME="pgfId=916"></A>unary operators</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=917"></A>+ - * /</TD><TD><P CLASS="CellBody"><A NAME="pgfId=918"></A>arithmetic</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=919"></A>> >= < <=</TD><TD><P CLASS="CellBody"><A NAME="pgfId=920"></A>relational</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=921"></A>! && ||</TD><TD><P CLASS="CellBody"><A NAME="pgfId=924"></A>logical</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=925"></A>== !=</TD><TD><P CLASS="CellBody"><A NAME="pgfId=926"></A>logical equality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=927"></A>?:</TD><TD><P CLASS="CellBody"><A NAME="pgfId=928"></A>conditional</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=929"></A>or</TD><TD><P CLASS="CellBody"><A NAME="pgfId=930"></A>event</TD></TR></TABLE><P CLASS="Body"><A NAME="pgfId=934"></A>The result of using logical or relationaloperators on real numbers is a single-bit scalar value.</P><P><P CLASS="Body"><A NAME="pgfId=803"></A><A HREF="#pgfId=514">Table 4-3</A><P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2"><CAPTION ALIGN="TOP"><P CLASS="TableTitle"><A NAME="pgfId=514"></A>Table 4-3: Operatorsnot allowed for real expressions</CAPTION><TR><TD><P CLASS="CellBody"><A NAME="pgfId=541"></A>{}, {{}}</TD><TD><P CLASS="CellBody"><A NAME="pgfId=542"></A>concatenate, replicate</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=543"></A>%</TD><TD><P CLASS="CellBody"><A NAME="pgfId=544"></A>modulus</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=545"></A>=== !==</TD><TD><P CLASS="CellBody"><A NAME="pgfId=546"></A>case equality</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=579"></A>~ & | <BR>^ ^~ ~^</TD><TD><P CLASS="CellBody"><A NAME="pgfId=774"></A>bit-wise</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=797"></A>^ ^~ ~^<BR>& ~& | ~|</TD><TD><P CLASS="CellBody"><A NAME="pgfId=798"></A>reduction</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=799"></A><< >></TD><TD><P CLASS="CellBody"><A NAME="pgfId=800"></A>shift</TD></TR></TABLE><P CLASS="Body"><A NAME="pgfId=550"></A>See section 3.9.1 for moreinformation on use of real numbers.</P><P><P CLASS="SubSection"><A NAME="pgfId=548"></A>Binary operator precedence</P><P><P CLASS="Body"><A NAME="pgfId=497"></A>The precedence order of <I>binaryoperators</I> and the <I>conditional operator</I> (<B> ?:</B> ) is shownbelow in <A HREF="#pgfId=553">Table 4-4</A>. Verilog HDL has two equalityoperators. They are discussed in section 4.1.8.</P><P><TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2"><CAPTION ALIGN="TOP"><P CLASS="TableTitle"><A NAME="pgfId=553"></A>Table 4-4: Precedencerules for operators</CAPTION><TR><TD><P CLASS="CellBody"><A NAME="pgfId=801"></A>+ - ! ~ (unary)</TD><TD><P CLASS="CellBody"><A NAME="pgfId=802"></A>highest precedence</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=804"></A>* / %</TD><TD ROWSPAN="10"><P><P CLASS="CellBody"><A NAME="pgfId=809"></A> </P><P><IMG SRC="ch04-1.gif" WIDTH="13" HEIGHT="106" NATURALSIZEFLAG="3" ALIGN="BOTTOM"></TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=808"></A>+ - (binary)</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=816"></A><< >></TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=818"></A>< <= > >=</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=901"></A> == != === !==</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=903"></A> & ~&</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=1022"></A> ^ ^~</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=1038"></A> | ~|</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=1040"></A> &&</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=1042"></A> ||</TD></TR><TR><TD><P CLASS="CellBody"><A NAME="pgfId=1044"></A> ?: (conditional operator)</TD><TD><P CLASS="CellBody"><A NAME="pgfId=1045"></A>lowest precedence</TD></TR></TABLE><P CLASS="Body"><A NAME="pgfId=556"></A>Operators shown on the same rowin <A HREF="#pgfId=553">Table 4-4</A> shall have the same precedence.Rows are arranged in order of decreasing precedence for the operators. Forexample,<B> </B>*, /, and % all have the same precedence, which is higherthan that of the binary + and - operators.</P><P><P CLASS="Body"><A NAME="pgfId=557"></A>All operators shall associateleft to right with the exception of the conditional operator which shallassociate right to left. Associativity refers to the order in which theoperators having the same precedence are evaluated. Thus, in the followingexample <CODE>B</CODE> is added to <CODE>A</CODE> and then <CODE>C</CODE>is subtracted from the result of <CODE>A+B</CODE> .</P><PRE> A + B - C</PRE><P><P CLASS="Body"><A NAME="pgfId=559"></A>When operators differ in precedence,the operators with higher precedence shall associate first. In the followingexample, <CODE>B</CODE> is divided by <CODE>C</CODE> (division has higherprecedence than addition) and then the result is added to <CODE>A</CODE>.</P><PRE> A + B / C</PRE><P><P CLASS="Body"><A NAME="pgfId=561"></A>Parentheses can be used to changethe operator precedence.</P><PRE> (A + B) / C // not the same as A + B / C</PRE><P><P CLASS="SubSection"><A NAME="pgfId=563"></A>Using integer numbers inexpressions</P><P><P CLASS="Body"><A NAME="pgfId=906"></A>Integer numbers can be used asoperands in expressions. An integer number can be expressed as</P><UL> <LI><A NAME="pgfId=907"></A>an unsized, unbased integer (e.g. 12) <LI><A NAME="pgfId=908"></A>an unsized, based integer (e.g. `d12) <LI><A NAME="pgfId=502"></A>a sized, based integer (e.g. 16'd12)</UL><P><P CLASS="Body"><A NAME="pgfId=530"></A>A negative value for an integerwith no base specifier shall be interpreted differently than for an integerwith a base specifier. An integer with no base specifier shall be interpretedas a signed value in two's complement form. An integer with a base specifiershall be interpreted as an unsigned value in two's complement form.</P><H2> </H2><P><P CLASS="Body"><A NAME="pgfId=937"></A>This example shows two ways towrite the expression "minus 12 divided by 3". Note that <CODE>-12</CODE>and <CODE>-'d12</CODE> both evaluate to the same two's complement bit patternbut in an expression, the <CODE>-'d12</CODE> loses its identity as a signednegative number.</P><PRE><B>integer</B> IntA;IntA = -12 / 3; // The result is -4IntA = -'d 12 / 3; // The result is 1431655761.</PRE><P><P CLASS="SubSection"><A NAME="pgfId=564"></A>Expression evaluation order</P><P><P CLASS="Body"><A NAME="pgfId=715"></A>The operators shall follow theassociativity rules while evaluating an expression as described in section 4.1.2.However, if the final result of an expression can be determined early, theentire expression need not be evaluated. This is called <I>short-circuiting</I>an expression evaluation.</P><PRE><B>reg</B> regA, regB, regC, result ;result = regA & (regB | regC) ;</PRE><P><P CLASS="Body"><A NAME="pgfId=788"></A>If regA is known to be zero,?? 快捷鍵說明
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