?? top.rpt
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Project Information d:\fast_adc\top.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/27/2007 16:49:55
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
top EPM7064SLC44-10 4 18 8 40 43 62 %
User Pins: 4 18 8
Project Information d:\fast_adc\top.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
top@27 AD0
top@28 AD1
top@29 AD2
top@31 AD3
top@34 AD4
top@33 AD5
top@36 AD6
top@37 AD7
top@39 AD8
top@40 AD9
top@4 AD10
top@5 AD11
top@6 AD12
top@8 AD13
top@9 AD14
top@43 ALE
top@1 A15
top@11 CK_out
top@17 P00
top@18 P01
top@19 P02
top@20 P03
top@21 P04
top@24 P05
top@25 P06
top@26 P07
top@14 RAM_RD
top@44 RD
top@12 STATE_out
top@2 WR
Project Information d:\fast_adc\top.rpt
** FILE HIERARCHY **
|74273b:18|
|mcu_ctrl:21|
|mcu_ctrl:21|74373:112|
|mcu_ctrl:21|74154:116|
|bus8:31|
|bus8:31|lpm_bustri:lpm_bustri_component|
|clk_sel:49|
|clk_sel:49|lpm_mux:lpm_mux_component|
|clk_sel:49|lpm_mux:lpm_mux_component|bypassff:sel_latency_ff0|
|clk_sel:49|lpm_mux:lpm_mux_component|altshift:external_latency_ffs|
|clk_sel:49|lpm_mux:lpm_mux_component|muxlut:61|
|clk_sel:49|lpm_mux:lpm_mux_component|muxlut:61|muxlut:45|
|clk_sel:49|lpm_mux:lpm_mux_component|muxlut:61|muxlut:64|
|clk_sel:49|lpm_mux:lpm_mux_component|muxlut:61|muxlut:83|
|div_clk:54|
|counter15:58|
|counter15:58|lpm_counter:lpm_counter_component|
Device-Specific Information: d:\fast_adc\top.rpt
top
***** Logic for device 'top' compiled without errors.
Device: EPM7064SLC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R
E
S
E
A A A R
D D D V A A G V A
1 1 1 C W 1 R L N E D
2 1 0 C R 5 D E D D 9
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | AD8
AD13 | 8 38 | #TDO
AD14 | 9 37 | AD7
GND | 10 36 | AD6
CK_out | 11 35 | VCC
STATE_out | 12 EPM7064SLC44-10 34 | AD4
#TMS | 13 33 | AD5
RAM_RD | 14 32 | #TCK
VCC | 15 31 | AD3
RESERVED | 16 30 | GND
P00 | 17 29 | AD2
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
P P P P G V P P P A A
0 0 0 0 N C 0 0 0 D D
1 2 3 4 D C 5 6 7 0 1
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\fast_adc\top.rpt
top
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 11/16( 68%) 8/ 8(100%) 11/16( 68%) 36/36(100%)
B: LC17 - LC32 13/16( 81%) 7/ 8( 87%) 9/16( 56%) 25/36( 69%)
C: LC33 - LC48 7/16( 43%) 8/ 8(100%) 12/16( 75%) 27/36( 75%)
D: LC49 - LC64 9/16( 56%) 7/ 8( 87%) 11/16( 68%) 30/36( 83%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 30/32 ( 93%)
Total logic cells used: 40/64 ( 62%)
Total shareable expanders used: 43/64 ( 67%)
Total Turbo logic cells used: 40/64 ( 62%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 14.62
Total fan-in: 585
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 18
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 40
Total flipflops required: 31
Total product terms required: 140
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 20
Synthesized logic cells: 2/ 64 ( 3%)
Device-Specific Information: d:\fast_adc\top.rpt
top
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT 0 0 0 0 0 15 13 ALE
1 - - INPUT 0 0 0 0 0 24 1 A15
17 24 B BIDIR 1 1 0 3 5 15 1 P00 (|74273b:18|:19)
18 21 B BIDIR 1 1 0 3 5 16 0 P01 (|74273b:18|:18)
19 20 B BIDIR 1 1 0 2 6 1 1 P02 (|74273b:18|:17)
20 19 B BIDIR 1 1 0 2 6 1 1 P03 (|74273b:18|:16)
21 17 B BIDIR 1 1 0 3 5 15 1 P04 (|74273b:18|:15)
24 33 C BIDIR 1 1 0 3 5 15 1 P05 (|74273b:18|:14)
25 35 C BIDIR 1 1 0 3 5 15 1 P06 (|74273b:18|:13)
26 36 C BIDIR 1 1 0 2 6 1 0 P07 (|74273b:18|:12)
44 - - INPUT 0 0 0 0 0 16 1 RD
2 - - INPUT 0 0 0 0 0 8 0 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\top.rpt
top
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
27 37 C FF t 9 9 0 3 17 15 0 AD0
28 40 C FF t 11 11 0 3 18 14 0 AD1
29 41 C FF t 11 11 0 3 19 13 0 AD2
31 46 C FF t 11 11 0 3 20 12 0 AD3
34 51 D FF t 11 11 0 3 21 11 0 AD4
33 49 D FF t 11 11 0 3 22 10 0 AD5
36 52 D FF t 11 11 0 3 23 9 0 AD6
37 53 D FF t 11 11 0 3 24 8 0 AD7
39 57 D FF t 11 11 0 3 25 7 0 AD8
40 62 D FF t 11 11 0 3 26 6 0 AD9
4 16 A FF t 11 11 0 3 27 5 0 AD10
5 14 A FF t 11 11 0 3 28 4 0 AD11
6 11 A FF t 11 11 0 3 29 3 0 AD12
8 5 A FF t 11 11 0 3 30 2 0 AD13
9 4 A FF t 11 11 0 3 31 1 0 AD14
11 3 A OUTPUT t 0 0 0 0 1 0 0 CK_out
17 24 B TRI/FF t 1 1 0 3 5 15 1 P00 (|74273b:18|:19)
18 21 B TRI/FF t 1 1 0 3 5 16 0 P01 (|74273b:18|:18)
19 20 B TRI/FF t 1 1 0 2 6 1 1 P02 (|74273b:18|:17)
20 19 B TRI/FF t 1 1 0 2 6 1 1 P03 (|74273b:18|:16)
21 17 B TRI/FF t 1 1 0 3 5 15 1 P04 (|74273b:18|:15)
24 33 C TRI/FF t 1 1 0 3 5 15 1 P05 (|74273b:18|:14)
25 35 C TRI/FF t 1 1 0 3 5 15 1 P06 (|74273b:18|:13)
26 36 C TRI/FF t 1 1 0 2 6 1 0 P07 (|74273b:18|:12)
14 30 B OUTPUT t 0 0 0 2 5 0 0 RAM_RD
12 1 A FF t 0 0 0 0 16 0 0 STATE_out
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