/***********************************************************************/
/*                                                                     */
/*   MODULE:  BDTest/sysconf.h                                         */
/*   DATE:    98/05/13                                                 */
/*   PURPOSE: SNDS Board System Configuration header file              */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*      Copyright (C) 1997 Samsung Electronics.                        */
/*                                                                     */
/***********************************************************************/

#ifndef  _SYSCONF_H
#define  _SYSCONF_H

#define DEBUG   0           /* DEBUG mode */


/*=====================================================================*/
/*                                                                     */
/*                     SYSTEM CLOCK CONTROL                            */
/*                                                                     */
/*   * fMCLK   SYSTEM CLOCK Oscillator frequency                       */
/*   * REF_CYCLE  Unit[ms], Default refresh cycle is 14ms              */
/*                                                                     */
/*=====================================================================*/
#define MHz      1000000

#define fMCLK                 50*MHz       
#define MCLK2                 (fMCLK/2)

#define Delay4ClkCange    100      //Delay for clock stabilization when
                                   //CPU clock change
#define REF_CYCLE          16      //Unit[ms]. default refresh cycle 16ms. 


/*=====================================================================*/
/*                                                                     */
/*                      DRAM MEMORY                                    */
/*                                                                     */
/*                                                                     */
/*=====================================================================*/
#define DownLoadArea	0x1000050   //User code down load area
#define MemCopySrc      0x1100000
#define MemTestLoop     5           //default memory test counter
#define TestPattern     0x5a5a5a5a


/*=====================================================================*/
/*                                                                     */
/*                        E E P R O M                                  */
/*                                                                     */
/*                                                                     */
/*=====================================================================*/
//#define _B0SIZE   B0SIZE_SHORT       // Select Bank0 bus width,Must be same
                                     // value of B0SIZE pin option
#define EEPROM_BufferArea 0x1200000  // EEPROM buffer for fusing
#define EEPROM_WriteArea  0x0000000  // EEPROM Write area


/*=====================================================================*/
/*                                                                     */
/*                      CACHE & INTERNAL SRAM                          */
/*                                                                     */
/*   * InterSramArea   Internal SRAM base address                      */
/*   * CACHE_4K        4K cache, 4k SRAM                               */
/*   * CACHE_8K        8K cache                                        */
/*   * CACHE_OFF       8K cache memory can be used to SRAM             */
/*                                                                     */
/*   % All cases at the above, Write buffer is enabled and             */
/*     Stall disabled.                                                 */
/*                                                                     */
/*=====================================================================*/
#define InterSramArea         0x3fe0000  
#define CACHE_4K              0x0  
#define CACHE_8K              0x1  
#define CACHE_OFF             0x2  


/*=====================================================================*/
/*                                                                     */
/*                    G D M A (General DMA)                            */
/*                                                                     */
/*=====================================================================*/
#define DmaTestSize     0x0010000
#define DmaTestSrc      0x5100000
#define DmaTestDest     0x5200000
#define DmaTestLoop     5
#define DmaTestPattern  0x5a5a5a5a
#define NonCachingArea(x) (x|=0x4000000)
#define DmaCodeArea     0x1400000

/*=====================================================================*/
/*                                                                     */
/*                 SERIAL CHANNEL ( UART0/UART1 )                      */
/*                                                                     */
/*  *BAUD : Default UART baudrate value.                               */
/*          Currently, used system clock,fMCLK,is 29.4912MHz.          */
/*          If fMCLK need to be changed then baudrate table in serial.c*/
/*          have to be updated according to it.                        */
/*=====================================================================*/
#define baudrate       115200     /* 115200bps UART baudrate */  
#define UartTxbuff     0x1100000  /*UART external loopback test Tx buffer */
#define UartRxbuff     0x1200000  /*UART external loopback test Rx buffer*/ 
#define UartTestSize   0x0000100  /*Loopback test buffer size(byte)*/

/*=====================================================================*/
/*                                                                     */
/*                            IIC  BUS                                 */
/*                                                                     */
/*   * 64Kbit IIC Bus EEPROM                                           */
/*   * fSCL =  400000 : 400KHz IIC Serial clock frequency              */
/*                                                                     */
/*=====================================================================*/
#define   fSCL         100000     /* IIC Serial clock frequency */
                                  /* = 700KHz */

/*=====================================================================*/
/*                                                                     */
/*                            TIMER                                    */
/*                                                                     */
/*=====================================================================*/
/* This is the number of timer ticks that occur per second. */
#define TICKS_PER_SECOND        100

/* Number of ticks for one second  */
#define ONE_SECOND              1000    /* In case of time unit[ms] */


#endif