/* -----------------------------------------------------------------------------
def21160.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21160

This include file contains a list of macro "defines" to enable the programmer
to use symbolic names for the following ADSP-21160 facilities:
 - instruction condition codes
 - system register bit definitions
 - IOP register map
 - *some* IOP register bit definitions

Here are some example uses:

   bit set mode1 BR0|IRPTEN|ALUSTAT;

   ustat1=BSO|HPM01|HMSWF;
   DM(SYSCON)=ustat1;

--------------------------------------------------------------------------------*/
 
/*------------------------------------------------------------------------------*/
/*                System Register bit definitions                             	*/
/*------------------------------------------------------------------------------*/
/* MODE1 and MMASK registers */
#define	BR8		0x00000001	/* Bit  0: Bit-reverse for I8						*/
#define	BR0		0x00000002	/* Bit  1: Bit-reverse for I0 (uses DMS0- only )	*/
#define	SRCU	0x00000004	/* Bit  2: Alt. register select for comp. units		*/
#define	SRD1H	0x00000008	/* Bit  3: DAG1 alt. register select (7-4)			*/
#define	SRD1L	0x00000010	/* Bit  4: DAG1 alt. register select (3-0)			*/
#define	SRD2H	0x00000020	/* Bit  5: DAG2 alt. register select (15-12)		*/
#define	SRD2L	0x00000040	/* Bit  6: DAG2 alt. register select (11-8)			*/
#define	SRRFH	0x00000080	/* Bit  7: Register file alt. select for R(15-8)	*/
#define	SRRFL	0x00000400	/* Bit 10: Register file alt. select for R(7-0)		*/
#define	NESTM	0x00000800	/* Bit 11: Interrupt nesting enable					*/
#define	IRPTEN	0x00001000	/* Bit 12: Global interrupt enable					*/
#define	ALUSAT	0x00002000	/* Bit 13: Enable ALU fixed-pt. saturation			*/
#define	SSE		0x00004000	/* Bit 14: Enable short word sign extension			*/
#define	TRUNC	0x00008000	/* Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest	*/
#define	RND32	0x00010000	/* Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd	*/
#define	CSEL	0x00060000	/* Bit 17-18: CSelect: Bus Mastership			   	*/
#define	PEYEN	0x00200000	/* Bit 21: Processing Element Y enable			   	*/
#define	SIMD	0x00200000	/* Bit 21: Enable SIMD Mode						   	*/
#define	BDCST9	0x00400000	/* Bit 22: Load Broadcast for I9				   	*/
#define	BDCST1	0x00800000	/* Bit 23: Load Broadcast for I1				   	*/
#define	CBUFEN	0x01000000	/* Bit 23: Circular Buffer Enable				   	*/

/* MODE2 register */
#define	IRQ0E	0x00000001	/* Bit  0: IRQ0- 1=edge sens. 0=level sens.		   	*/
#define	IRQ1E	0x00000002	/* Bit  1: IRQ1- 1=edge sens. 0=level sens.		   	*/
#define	IRQ2E	0x00000004	/* Bit  2: IRQ2- 1=edge sens. 0=level sens.		   	*/
#define	CADIS	0x00000010	/* Bit  4: Cache disable						   	*/
#define	TIMEN	0x00000020	/* Bit  5: Timer enable                            	*/
#define	BUSLK	0x00000040	/* Bit  6: External bus lock                       	*/
#define	FLG0O	0x00008000	/* Bit 15: FLAG0 1=output 0=input                  	*/
#define	FLG1O	0x00010000	/* Bit 16: FLAG1 1=output 0=input                  	*/
#define	FLG2O	0x00020000	/* Bit 17: FLAG2 1=output 0=input                  	*/
#define	FLG3O	0x00040000	/* Bit 18: FLAG3 1=output 0=input                  	*/
#define	CAFRZ	0x00080000	/* Bit 19: Cache freeze                            	*/
#define	IIRAE	0x00100000	/* Bit 20: Illegal IOP Register Access Enable      	*/
#define	U64MAE	0x00200000	/* Bit 21: Unaligned 64-bit Memory Access Enable   	*/
/* bits 31-30, 27-25 are Processor ID[4:0], read only, value: 0b01001
   bits 29-28    are silicon revision[1:0], read only, value: 0

   These bits (only) are routed to Mode2 Shadow register (IOP register ox11)
*/

/* FLAGS register */
#define FLG0    0x00000001 /* Bit 0: FLAG0 value                              	*/
#define FLG1    0x00000002 /* Bit 1: FLAG1 value                              	*/
#define FLG2    0x00000004 /* Bit 2: FLAG2 value                              	*/
#define FLG3    0x00000008 /* Bit 2: FLAG3 value                              	*/

/* ASTATx and ASTATy registers */
#define AZ      0x00000001 /* Bit  0: ALU result zero or fltg-pt. underflow   	*/
#define AV      0x00000002 /* Bit  1: ALU overflow                            	*/
#define AN      0x00000004 /* Bit  2: ALU result negative                     	*/
#define AC      0x00000008 /* Bit  3: ALU fixed-pt. carry                     	*/
#define AS      0x00000010 /* Bit  4: ALU X input sign (ABS and MANT ops)     	*/
#define AI      0x00000020 /* Bit  5: ALU fltg-pt. invalid operation          	*/
#define MN      0x00000040 /* Bit  6: Multiplier result negative              	*/
#define MV      0x00000080 /* Bit  7: Multiplier overflow                     	*/
#define MU      0x00000100 /* Bit  8: Multiplier fltg-pt. underflow           	*/
#define MI      0x00000200 /* Bit  9: Multiplier fltg-pt. invalid operation   	*/
#define AF      0x00000400 /* Bit 10: ALU fltg-pt. operation                  	*/
#define SV      0x00000800 /* Bit 11: Shifter overflow                        	*/
#define SZ      0x00001000 /* Bit 12: Shifter result zero                    	*/
#define SS      0x00002000 /* Bit 13: Shifter input sign                      	*/
#define BTF     0x00040000 /* Bit 18: Bit test flag for system registers      	*/
#define CACC0   0x01000000 /* Bit 24: Compare Accumulation Bit 0              	*/
#define CACC1   0x02000000 /* Bit 25: Compare Accumulation Bit 1              	*/
#define CACC2   0x04000000 /* Bit 26: Compare Accumulation Bit 2              	*/
#define CACC3   0x08000000 /* Bit 27: Compare Accumulation Bit 3              	*/
#define CACC4   0x10000000 /* Bit 28: Compare Accumulation Bit 4              	*/
#define CACC5   0x20000000 /* Bit 29: Compare Accumulation Bit 5              	*/
#define CACC6   0x40000000 /* Bit 30: Compare Accumulation Bit 6              	*/
#define CACC7   0x80000000 /* Bit 31: Compare Accumulation Bit 7              	*/

/* STKYx and STKYy registers */
#define AUS     0x00000001 /* Bit  0: ALU fltg-pt. underflow                  	*/
#define AVS     0x00000002 /* Bit  1: ALU fltg-pt. overflow                   	*/
#define AOS     0x00000004 /* Bit  2: ALU fixed-pt. overflow                  	*/ 
#define AIS     0x00000020 /* Bit  5: ALU fltg-pt. invalid operation          	*/
#define MOS     0x00000040 /* Bit  6: Multiplier fixed-pt. overflow           	*/
#define MVS     0x00000080 /* Bit  7: Multiplier fltg-pt. overflow            	*/
#define MUS     0x00000100 /* Bit  8: Multiplier fltg-pt. underflow           	*/
#define MIS     0x00000200 /* Bit  9: Multiplier fltg-pt. invalid operation   	*/
#define CB7S    0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow         	*/
#define CB15S   0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow        	*/
#define PCFL    0x00200000 /* Bit 21: PC stack full                           	*/
#define PCEM    0x00400000 /* Bit 22: PC stack empty                          	*/
#define SSOV    0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT) 	*/
#define SSEM    0x01000000 /* Bit 24: Status stack empty                      	*/
#define LSOV    0x02000000 /* Bit 25: Loop stack overflow                     	*/
#define LSEM    0x04000000 /* Bit 26: Loop stack empty                        	*/

/* STKYx register *ONLY* */
#define IIRA    0x00080000 /* Bit 19: Illegal IOP Register Access             	*/
#define U64MA   0x00100000 /* Bit 20: Unaligned 64-bit Memory Access          	*/

/* IRPTL and IMASK and IMASKP registers */
#define EMUI    0x00000001 /* Bit  0: Offset: 00: Emulator Interrupt          	*/
#define RSTI    0x00000002 /* Bit  1: Offset: 04: Reset                       	*/
#define IICDI   0x00000004 /* Bit  2: Offset: 08: Illegal Input Condition Detected */
#define SOVFI   0x00000008 /* Bit  3: Offset: 0c: Stack overflow              	*/
#define TMZHI   0x00000010 /* Bit  4: Offset: 10: Timer = 0 (high priority)   	*/
#define VIRPTI  0x00000020 /* Bit  5: Offset: 14: Vector interrupt            	*/
#define IRQ2I   0x00000040 /* Bit  6: Offset: 18: IRQ2- asserted              	*/
#define IRQ1I   0x00000080 /* Bit  7: Offset: 1c: IRQ1- asserted              	*/
#define IRQ0I   0x00000100 /* Bit  8: Offset: 20: IRQ0- asserted              	*/
#define SPR0I	0x00000400 /* Bit 10: Offset: 28: SPORT0 receive DMA channel  	*/
#define SPR1I	0x00000800 /* Bit 11: Offset: 2c: SPORT1 receive DMA channel  	*/
#define SPT0I	0x00001000 /* Bit 12: Offset: 30: SPORT0 transmit DMA channel 	*/
#define SPT1I	0x00002000 /* Bit 13: Offset: 34: SPORT1 transmit DMA channel 	*/
#define LPISUMI	0x00004000 /* Bit 14: Offset: na: LPort Interrupt Summary     	*/
#define EP0I	0x00008000 /* Bit 15: Offset: 50: External port channel 0 DMA 	*/
#define EP1I	0x00010000 /* Bit 16: Offset: 54: External port channel 1 DMA 	*/
#define EP2I	0x00020000 /* Bit 17: Offset: 58: External port channel 2 DMA 	*/
#define EP3I	0x00040000 /* Bit 18: Offset: 5c: External port channel 3 DMA 	*/
#define LSRQI	0x00080000 /* Bit 19: Offset: 60: Link service request	      	*/
#define CB7I    0x00100000 /* Bit 20: Offset: 64: Circ. buffer 7 overflow     	*/
#define CB15I   0x00200000 /* Bit 21: Offset: 68: Circ. buffer 15 overflow    	*/
#define TMZLI   0x00400000 /* Bit 22: Offset: 6c: Timer = 0 (low priority)    	*/
#define FIXI    0x00800000 /* Bit 23: Offset: 70: Fixed-pt. overflow          	*/
#define FLTOI   0x01000000 /* Bit 24: Offset: 74: fltg-pt. overflow           	*/
#define FLTUI   0x02000000 /* Bit 25: Offset: 78: fltg-pt. underflow          	*/
#define FLTII   0x04000000 /* Bit 26: Offset: 7c: fltg-pt. invalid            	*/
#define SFT0I   0x08000000 /* Bit 27: Offset: 80: user software int 0         	*/
#define SFT1I   0x10000000 /* Bit 28: Offset: 84: user software int 1         	*/
#define SFT2I   0x20000000 /* Bit 39: Offset: 88: user software int 2         	*/
#define SFT3I   0x40000000 /* Bit 30: Offset: 8c: user software int 3         	*/

/* LIRPTL register */
#define LP0I	0x00000001 /* Bit  0: Offset: 38: Link port channel 0 DMA 		*/
#define LP1I	0x00000002 /* Bit  1: Offset: 3C: Link port channel 1 DMA 		*/
#define LP2I	0x00000004 /* Bit  2: Offset: 40: Link port channel 2 DMA 		*/