?? def21160.h
字號:
#define LP3I 0x00000008 /* Bit 3: Offset: 44: Link port channel 3 DMA */
#define LP4I 0x00000010 /* Bit 4: Offset: 48: Link port channel 4 DMA */
#define LP5I 0x00000020 /* Bit 5: Offset: 4C: Link port channel 5 DMA */
#define LP0MSK 0x00010000 /* Bit 16: Link port channel 0 Interrupt Mask */
#define LP1MSK 0x00020000 /* Bit 17: Link port channel 1 Interrupt Mask */
#define LP2MSK 0x00040000 /* Bit 18: Link port channel 2 Interrupt Mask */
#define LP3MSK 0x00080000 /* Bit 19: Link port channel 3 Interrupt Mask */
#define LP4MSK 0x00100000 /* Bit 20: Link port channel 4 Interrupt Mask */
#define LP5MSK 0x00200000 /* Bit 21: Link port channel 5 Interrupt Mask */
#define LP0MSKP 0x01000000 /* Bit 24: Link port channel 0 Interrupt Mask Pointer*/
#define LP1MSKP 0x02000000 /* Bit 25: Link port channel 1 Interrupt Mask Pointer*/
#define LP2MSKP 0x04000000 /* Bit 26: Link port channel 2 Interrupt Mask Pointer*/
#define LP3MSKP 0x08000000 /* Bit 27: Link port channel 3 Interrupt Mask Pointer*/
#define LP4MSKP 0x10000000 /* Bit 28: Link port channel 4 Interrupt Mask Pointer*/
#define LP5MSKP 0x20000000 /* Bit 29: Link port channel 5 Interrupt Mask Pointer*/
/*------------------------------------------------------------------------------*/
/* I/O Processor Register Map */
/*------------------------------------------------------------------------------*/
#define SYSCON 0x00 /* System configuration register */
#define VIRPT 0x01 /* Vector interrupt register */
#define WAIT 0x02 /* External Port Wait register - renamed to EPCON */
#define EPCON 0x02 /* External Port configuration register */
#define SYSTAT 0x03 /* System status register */
/* the upper 32-bits of the 64-bit epbxs are only accessible as 64-bit reference*/
#define EPB0 0x04 /* External port DMA buffer 0 */
#define EPB1 0x06 /* External port DMA buffer 1 */
#define MSGR0 0x08 /* Message register 0 */
#define MSGR1 0x09 /* Message register 1 */
#define MSGR2 0x0a /* Message register 2 */
#define MSGR3 0x0b /* Message register 3 */
#define MSGR4 0x0c /* Message register 4 */
#define MSGR5 0x0d /* Message register 5 */
#define MSGR6 0x0e /* Message register 6 */
#define MSGR7 0x0f /* Message register 7 */
/* IOP shadow registers of the core control regs */
#define PC_SHDW 0x10 /* PC IOP shadow register (PC[23-0]) */
#define MODE2_SHDW 0x11 /* Mode2 IOP shadow register (MODE2[31-25]) */
#define EPB2 0x14 /* EXternal port DMA buffer 2 */
#define EPB3 0x16 /* External port DMA buffer 3 */
#define BMAX 0x18 /* Bus time-out maximum */
#define BCNT 0x19 /* Bus time-out counter */
#define ELAST 0x1b /* Address of last external access for page detect */
#define DMAC10 0x1c /* EP DMA10 control register */
#define DMAC11 0x1d /* EP DMA11 control register */
#define DMAC12 0x1e /* EP DMA12 control register */
#define DMAC13 0x1f /* EP DMA13 Control register */
#define II4 0x30 /* Internal DMA4 memory address */
#define IM4 0x31 /* Internal DMA4 memory access modifier */
#define C4 0x32 /* Contains number of DMA4 transfers remaining */
#define CP4 0x33 /* Points to next DMA4 parameters */
#define GP4 0x34 /* DMA4 General purpose / 2-D DMA */
#define DB4 0x35 /* DMA4 General purpose / 2-D DMA */
#define DA4 0x36 /* DMA4 General purpose / 2-D DMA */
#define DMASTAT 0x37 /* DMA channel status register */
#define II5 0x38 /* Internal DMA5 memory address */
#define IM5 0x39 /* Internal DMA5 memory access modifier */
#define C5 0x3a /* Contains number of DMA5 transfers remainnig */
#define CP5 0x3b /* Points to next DMA5 parameters */
#define GP5 0x3c /* DMA5 General purpose / 2-D DMA */
#define DB5 0x3d /* DMA5 General pu rpose / 2-D DMA */
#define DA5 0x3e /* DMA5 General purpose / 2-D DMA */
#define II10 0x40 /* Internal DMA10 memory address */
#define IM10 0x41 /* Internal DMA10 memory access modifier */
#define C10 0x42 /* Contains number of DMA10 transfers remainnig */
#define CP10 0x43 /* Points to next DMA10 parameters */
#define GP10 0x44 /* DMA10 General purpose */
#define EI10 0x45 /* External DMA10 address */
#define EM10 0x46 /* External DMA10 address modifier */
#define EC10 0x47 /* External DMA10 counter */
#define II11 0x48 /* Internal DMA11 memory address */
#define IM11 0x49 /* Internal DMA11 memory access modifier */
#define C11 0x4a /* Contains number of DMA11 transfers remainnig */
#define CP11 0x4b /* Points to next DMA11 parameters */
#define GP11 0x4c /* DMA11 General purpose */
#define EI11 0x4d /* External DMA11 address */
#define EM11 0x4e /* External DMA11 address modifier */
#define EC11 0x4f /* External DMA counter */
#define II12 0x50 /* Internal DMA12 memory address */
#define IM12 0x51 /* Internal DMA12 memory access modifier */
#define C12 0x52 /* Contains number of DMA12 transfers remainnig */
#define CP12 0x53 /* Points to next DMA12 parameters */
#define GP12 0x54 /* DMA12 General purpose */
#define EI12 0x55 /* External DMA12 address */
#define EM12 0x56 /* External DMA12 address modifier */
#define EC12 0x57 /* External DMA12 counter */
#define II13 0x58 /* Internal DMA13 memory address */
#define IM13 0x59 /* Internal DMA13 memory access modifier */
#define C13 0x5a /* Contains number of DMA13 transfers remainnig */
#define CP13 0x5b /* Points to next DMA13 parameters */
#define GP13 0x5c /* DMA13 General purpose */
#define EI13 0x5d /* External DMA13 address */
#define EM13 0x5e /* External DMA13 address modifier */
#define EC13 0x5f /* External DMA13 counter */
#define II0 0x60 /* Internal DMA0 memory address */
#define IM0 0x61 /* Internal DMA0 memory access modifier */
#define C0 0x62 /* Contains number of DMA0 transfers remainnig */
#define CP0 0x63 /* Points to next DMA0 parameters */
#define GP0 0x64 /* DMA0 General purpose / 2-D DMA */
#define DB0 0x65 /* DMA0 General purpose / 2-D DMA */
#define DA0 0x66 /* DMA0 General purpose / 2-D DMA */
#define II1 0x68 /* Internal DMA1 memory address */
#define IM1 0x69 /* Internal DMA1 memory access modifier */
#define C1 0x6a /* Contains number of DMA1 transfers remainnig */
#define CP1 0x6b /* Points to next DMA1 parameters */
#define GP1 0x6c /* DMA1 General purpose / 2-D DMA */
#define DB1 0x6d /* DMA1 General purpose / 2-D DMA */
#define DA1 0x6e /* DMA1 General purpose / 2-D DMA */
#define II2 0x70 /* Internal DMA2 memory address */
#define IM2 0x71 /* Internal DMA2 memory access modifier */
#define C2 0x72 /* Contains number of DMA2 transfers remainnig */
#define CP2 0x73 /* Points to next DMA2 parameters */
#define GP2 0x74 /* DMA2 General purpose / 2-D DMA */
#define DB2 0x75 /* DMA2 General purpose / 2-D DMA */
#define DA2 0x76 /* DMA2 General purpose / 2-D DMA */
#define II3 0x78 /* Internal DMA3 memory address */
#define IM3 0x79 /* Internal DMA3 memory access modifier */
#define C3 0x7a /* Contains number of DMA3 transfers remainnig */
#define CP3 0x7b /* Points to next DMA3 parameters */
#define GP3 0x7c /* DMA3 General purpose / 2-D DMA */
#define DB3 0x7d /* DMA3 General purpose / 2-D DMA */
#define DA3 0x7e /* DMA3 General purpose / 2-D DMA */
#define II6 0x80 /* Internal DMA6 memory address */
#define IM6 0x81 /* Internal DMA6 memory access modifier */
#define C6 0x82 /* Contains number of DMA6 transfers remainnig */
#define CP6 0x83 /* Points to next DMA6 parameters */
#define GP6 0x84 /* DMA6 General purpose / 2-D DMA */
#define DB6 0x85 /* DMA6 General purpose / 2-D DMA */
#define DA6 0x86 /* DMA6 General purpose / 2-D DMA */
#define II7 0x88 /* Internal DMA7 memory address */
#define IM7 0x89 /* Internal DMA7 memory access modifier */
#define C7 0x8a /* Contains number of DMA7 transfers remainnig */
#define CP7 0x8b /* Points to next DMA7 parameters */
#define GP7 0x8c /* DMA7 General purpose / 2-D DMA */
#define DB7 0x8d /* DMA7 General purpose / 2-D DMA */
#define DA7 0x8e /* DMA7 General purpose / 2-D DMA */
#define II8 0x90 /* Internal DMA8 memory address */
#define IM8 0x91 /* Internal DMA8 memory access modifier */
#define C8 0x92 /* Contains number of DMA8 transfers remainnig */
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -