?? boot5402.lst
字號:
201
202 000028 F073 b parallel ; Otherwise, check other boot modes.
000029 0031+
203 *****************************************************************
204 * HPI boot mode selected through int2.
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 5
205 *****************************************************************
206 00002a HPI ; Else, this is an HPI boot, all
207 ; other boot modes are ignored.
208 00002a 7701 stm #int2msk, ifr ; Clear INT2_ bit in ifr.
00002b 0004
209
210 00002c 487F ldm HPIentry, a ; Get HPI entry vector.
211 00002d F844 bc hpiboot, aneq ; If not zero, HPI boot.
00002e 00C4+
212 00002f F073 b $-3 ; else, keep looping.
000030 002C+
213
214
215
216
217
218
219 *****************************************************************
220 * Check Parallel Boot
221 *****************************************************************
222 000031 parallel
223 000031 7761 stm #0h, @xentry ; initialize the entry point
000032 0000
224 000033 7762 stm #boot, @entry ;
000034 0000+
225 000035 7465 portr #0ffffh, @src ; read source address of boot table
000036 FFFF
226 000037 7165 mvdk @src, ar1 ; ar1 points at source memory (Data)
000038 0011
227 000039 1091 ld *ar1+, a ; load accumulator A with BRW
228 00003a F110 sub #10AAh, a, b ; check 16-bit Boot?
00003b 10AA
229 00003c F84D bc par16, beq ; a=010AAh
00003d 0115+
230 00003e F030 and #0ffh, a ; check acc AL = 08
00003f 00FF
231 000040 F110 sub #8h, a, b ; check 8-bit Boot?
000041 0008
232 000042 F84C bc chk_data, bneq ; a=08xxh
000043 004B+
233 000044 1091 ld *ar1+, a ; 8-bit mode, LSB
234 000045 F030 and #0ffh, a ; check acc AL = AAh
000046 00FF
235 000047 F010 sub #0AAh, a ; LSB = 0AAh?
000048 00AA
236 000049 F845 bc par08, aeq ; 8-bit Parallel Boot
00004a 00C5+
237 00004b 7711 chk_data stm #0FFFFh, ar1 ; check data memory 0xFFFF
00004c FFFF
238 00004d F495 nop ; prevent pipeline conflict
239 00004e F495 nop ;
240 00004f 1091 ld *ar1+, a ; load accumulator A with BRW
241 000050 8811 stlm a, ar1 ; ar1 point at source memory (Data)
242 000051 F495 nop ; prevent posibble pipeline conflic
243 000052 F495 nop ;
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 6
244 000053 1091 ld *ar1+, a ; load acculator A with BRW
245 000054 F110 sub #10AAh, a, b ; check 16-bit Boot?
000055 10AA
246 000056 F84D bc par16, beq ; a=010AAh
000057 0115+
247 000058 7711 stm #0FFFFh, ar1 ; check data memory 0xFFFF & 0xFFFE
000059 FFFF
248 00005a F495 nop ; prevent possible pipeline conflic
249 00005b F495 nop ;
250 00005c 1289 ldu *ar1-, a ; acc A <-- source address
251 00005d F030 and #0FFh, a ; 0 the high byte
00005e 00FF
252 00005f 6F81 add *ar1, 8, a ;
000060 0C08
253 000061 8811 stlm a, ar1 ;
254 000062 F495 nop ; prvent possible pipeline conflic
255 000063 F495 nop ;
256 000064 1091 ld *ar1+, a ; load accumulator A with BRW
257 000065 F030 and #0ffh, a ; check acc AL = 08h
000066 00FF
258 000067 F110 sub #8h, a, b ; check 8-bit Boot?
000068 0008
259 000069 F84C bc ser_ini, bneq ; acc A = 08xxh
00006a 0072+
260 00006b 1091 ld *ar1+, a ; 8-bit mode, LSB
261 00006c F030 and #0ffh, a ; check acc AL = AAh
00006d 00FF
262 00006e F010 sub #0AAh, a ; LSB = 0AAh?
00006f 00AA
263 000070 F845 bc par08, aeq ; 8-bit Parallel Boot
000071 00C5+
264
265 000072 ser_ini
266
267 ********************************************************************************
268 *
269 * Initialization for 5402 BSPs
270 *
271 ********************************************************************************
272 *
273 * 1. BSP0 is configured for 16-bit, BCLKX input, BFSX input.
274 *
275 ********************************************************************************
276 *
277 000072 7738 STM SPCR1_SUBADDR,SPSA0
000073 0000
278 000074 7739 STM #0000h,SPSD0 ; DISABLES RECEIVE.
000075 0000
279
280 000076 7738 STM SPCR2_SUBADDR,SPSA0
000077 0001
281 000078 7739 STM #0000h,SPSD0 ; DISABLES TRANSMIT.
000079 0000
282
283 00007a 7738 STM RCR1_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 7
00007b 0002
284 00007c 7739 STM #0040H,SPSD0
00007d 0040
285
286 00007e 7738 STM RCR2_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
00007f 0003
287 000080 7739 STM #0041H,SPSD0 ; Single Phase, 16-bit, No Compan,1bit Delay.
000081 0041
288
289 000082 7738 STM SRGR1_SUBADDR,SPSA0
000083 0006
290 000084 7739 STM #0000H,SPSD0 ; Clear the clkdiv and frame width.
000085 0000
291
292 000086 7738 STM SRGR2_SUBADDR,SPSA0
000087 0007
293 000088 7739 STM #0000H,SPSD0 ; Clksm=0 External source.
000089 0000
294
295 00008a 7738 STM PCR_SUBADDR,SPSA0
00008b 000E
296 00008c 7739 STM #0000H,SPSD0 ; BCLKX and FSX configured as inputs
00008d 0000
297
298 00008e 7738 STM SPCR1_SUBADDR,SPSA0
00008f 0000
299 000090 7739 STM #0001H,SPSD0 ; ENABLES RECEIVE.
000091 0001
300
301 ********************************************************************************
302 * 2. BSP1 is configured for 8-bit, clk input, fm input. *
303 ********************************************************************************
304 000092 7748 STM SPCR1_SUBADDR,SPSA1
000093 0000
305 000094 7749 STM #0000h,SPSD1 ; DISABLES RECEIVE.
000095 0000
306
307 000096 7748 STM SPCR2_SUBADDR,SPSA1
000097 0001
308 000098 7749 STM #0000h,SPSD1 ; DISABLES TRANSMIT.
000099 0000
309
310 00009a 7748 STM RCR1_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
00009b 0002
311 00009c 7749 STM #0000H,SPSD1
00009d 0000
312
313 00009e 7748 STM RCR2_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
00009f 0003
314 0000a0 7749 STM #0001H,SPSD1 ; Single Phase, 8-bit, No Compan,1bit Delay
0000a1 0001
315
316 0000a2 7748 STM SRGR1_SUBADDR,SPSA1
0000a3 0006
317 0000a4 7749 STM #0000H,SPSD1 ; Clear the clkdiv and frame width.
TMS320C54x COFF Assembler Version 3.50 Thu Feb 03 13:21:23 2000
Copyright (c) 1996-1999 Texas Instruments Incorporated
bootVC5402 PAGE 8
0000a5 0000
318
319 0000a6 7748 STM SRGR2_SUBADDR,SPSA1
0000a7 0007
320 0000a8 7749 STM #0000H,SPSD1 ; Clksm=0 External source.
0000a9 0000
321
322 0000aa 7748 STM PCR_SUBADDR,SPSA1
0000ab 000E
323 0000ac 7749 STM #0000H,SPSD1 ; BCLKX and FSX configured as inputs
0000ad 0000
324
325 0000ae 7748 STM SPCR1_SUBADDR,SPSA1
0000af 0000
326 0000b0 7749 STM #0001H,SPSD1 ; ENABLES RECEIVE.
0000b1 0001
327
328 ********************************************************************************
329 ***
330
331 0000b2 F6BD rsbx xf ; signal ready-to-receive
332 0000b3 6101 chk_ser bitf ifr, #400h ; check RINT1 flag
0000b4 0400
333 0000b5 F930 cc BSP1, tc ;
0000b6 0145+
334 0000b7 6101 bitf ifr, #10h ; check RINT0 flag
0000b8 0010
335 0000b9 F930 cc BSP0, tc ;
0000ba 013B+
336 0000bb F803 bc pasyini, bio ; check for I/O boot
0000bc 0237+
337 **************RDP***************
338 * Add HPI entry check here. *
339 ********************************
340 0000bd 487F ldm HPIentry, a ; Get HPI entry vector.
341 0000be F844 bc hpiboot, aneq ; If not zero, HPI boot.
0000bf 00C4+
342 0000c0 F073 b chk_ser ; else, keep looping.
0000c1 00B3+
343 ********************************
344
345 *****************************************************************
346 * End-boot, simply branch to source address
347 *****************************************************************
348 0000c2 endboot
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