#define MCtlRecd	0x0020
#define	MIntRx		0x0040
#define	MRx10Stat	0x0080
#define	MAllignErr	0x0100
#define	MCRCErr		0x0200
#define	MOverflow	0x0400
#define	MLongErr	0x0800
#define	MRxPar		0x2000
#define	MRxGood		0x4000
#define	MRxHalted	0x8000


// Tx/Rx common descriptor structure 
typedef struct FrameDescriptor {
	long unsigned int FrameDataPtr;
	long unsigned int Reserved; 	// cf: RX-reserved, TX-Reserved(25bits) + Control bits(7bits)
	long unsigned int StatusAndFrameLength;
	long unsigned int NextFrameDescriptor;
} sFrameDescriptor;



typedef struct ETH_HEADER {
	U8 DestinationAddr[6] ;
	U8 SourceAddr[6] ;
	U8 LengthOrType[2] ;
} etheader ;



typedef struct MACFrame {
	etheader 	Header ;
	U8 		LLCData[1506] ;
} /*__attribute__((packed))*/ sMACFrame;



// MAC Tx Error Structure
typedef struct MACTxStatus {
	long unsigned int MacTxGood ;
	long unsigned int ExCollErr ;
	long unsigned int TxDefferedErr ;
	long unsigned int sPaused ;
	long unsigned int UnderErr ;
	long unsigned int DeferErr ;
	long unsigned int NCarrErr ;
	long unsigned int sSQE ;
	long unsigned int LateCollErr ;
	long unsigned int TxParErr ;
	long unsigned int sTxHalted ;
} pMACTxStatus ;

// MAC Rx Error Structure
typedef struct MACRxStatus {
	U32 OvMaxSize ;
	U32 sCtlRecd ;
	U32 sRx10Stat ;
	U32 AllgnErr ;
	U32 sCRCErr ;
	U32 OverflowErr ;
	U32 sLongErr ;
	U32 RxParErr ;
	U32 sRxHalted ;
} pMACRxStatus ;


// BDMA Tx Error Structure
typedef struct BDMATxStatus {
	U32 BTxNLErr ;
	U32 BTxNOErr ;
	U32 BTxEmptyErr ;
} pBDMATxStatus ;


// BDMA Rx Error Structure
typedef struct BDMARxStatus {
	U32 BdmaRxCnt ;
	U32 BdmaRxGood ;
	U32 BRxNLErr ;
	U32 BRxNOErr ;
	U32 BRxMSOErr ;
} pBDMARxStatus ;

typedef struct userbuff {     //ren defined
    U32 length[UserBuffSize];     //ethernet數據包長度
    sMACFrame frame[UserBuffSize]; //ethernet包
    U32 rear;                     //尾指針
    U32 head;                     //頭指針
 }__attribute__((packed)) UserBuff;


/* ------------------------------------------ */
/*   PHY(ICS1890) Register Description        */
/* ------------------------------------------ */
/*	PHY_CNTL_REG   : 0x00                 */
/*	PHY_STATUS_REG : 0x01                 */
/*	PHY_ID_REG1    : 0x02                 */
/*	PHY_ID_REG2    : 0x03                 */
/*	PHY_ANA_REG    : 0x04                 */
/*	PHY_ANLPAR_REG : 0x05                 */
/*	PHY_ANE_REG    : 0x06                 */
/* 	PHY_ECNTL_REG1 : 0x10                 */
/*	PHY_QPDS_REG   : 0x11                 */
/*	PHY_10BOP_REG  : 0x12                 */
/* 	PHY_ECNTL_REG2 : 0x13                 */
/* ------------------------------------------ */
#define	PHY_CNTL_REG 	0x00
#define	PHY_STATUS_REG 	0x01
#define	PHY_ID_REG1    	0x02
#define	PHY_ID_REG2    	0x03
#define	PHY_ANA_REG    	0x04
#define	PHY_ANLPAR_REG 	0x05
#define	PHY_ANE_REG    	0x06
#define	PHY_ECNTL_REG1 	0x10
#define	PHY_QPDS_REG   	0x11
#define	PHY_10BOP_REG  	0x12
#define	PHY_ECNTL_REG2 	0x13

#define PHYHWADDR	0x20 /* PHY H/W Address is 0x1 */	
#define PHYREGWRITE	0x1 << 10	
#define MiiBusy		0x1 << 11	

/* PHY control register */
#define RESET_PHY	1 << 15
#define ENABLE_LOOPBACK	1 << 14
#define DR_100MB	1 << 13
#define ENABLE_AN	1 << 12
#define PHY_MAC_ISOLATE	1 << 10
#define RESTART_AN	1 << 9
#define PHY_FULLDUPLEX	1 << 8
#define PHY_COL_TEST	1 << 7

/* PHY Status register */
#define AN_COMPLETE	1 << 5


/* PHY Auto-negotiation Advertisement register */
#define DR100_TX_FULL	1 << 8
#define DR100_TX_HALF	1 << 7
#define DR10_TX_FULL	1 << 6
#define DR10_TX_HALF	1 << 5


/*
 * Initialize Ethernet and MAC controller
 */
extern void LanInitialize(void) ;
//extern void MacWatchdogInit(void) ;
extern void MacInitialize(void) ;
extern void TxFDInitialize(void) ;
extern void RxFDInitialize(void) ;
extern void ReadyMacTx(void) ;
extern void ReadyMacRx(void) ;
extern void GetMyMacAddr(void) ;
extern void EmptyReceiveBuffer(void);
/*
 * LAN Watch-Dog function
 */
//extern void Lan_WatchDog(void) ;

/*
 * Manage and initialize PHY
 */
extern void ResetPhyChip(void) ;
extern void MiiStationWrite(U32 PhyInAddr, U32 PhyAddr, U32 PhyWrData) ;
extern U32 MiiStationRead(U32 PhyInAddr, U32 PhyAddr) ;
extern void delay_physet(void) ;


/*
 * MAC and BDMA interrupt service routine
 */
extern void MAC_Tx_isr(void) ;
extern void MAC_Rx_isr(void) ;
extern void BDMA_Tx_isr(void) ;
extern void BDMA_Rx_isr(void) ;
extern void BdmaRxForSingleIsr(void) ;

/*
 * Send Packet
 */
extern int SendPacket(U8 *Data,int Size) ;
//extern void Eth_Multi_Transmit(void) ;
extern int Random_Pkt_Transmit(void) ;
//extern void TxMacFrame(void) ;
//extern void ControlFrameTransfer(void) ;
//extern void SingleTransfer(void) ;


/*
 * Receive Packet
 */
extern void GetRxFrameData(U8 *pFrameData, U32 FrameLength, U32 RxStatus) ;
extern void RxMacFrame(void) ;
extern void ReceivePacket( void); //ren 



 /* Loopback test
 */

extern void MacPollLoopBack(void) ;



extern void ShowFrame(sMACFrame *frame);
/*
 * MAC and BDMA configuration
 */
//extern void MacConfig(void) ;
//extern void ViewMacAndBdmaConfiguration(void) ;
//extern void ChangeMacAndBdmaConfiguration(void) ;
//清緩沖區
void ReceiveBuffer_init(void);
 
int  ReceiveBuffer_empty(void);    //判斷緩沖區是否空
       
int ReceiveBuffer_full(void);     //緩沖區是否滿
 
sMACFrame * ReceiveBuffer_read(void);   //讀一個數據,有可能出錯，要注意 
 
        
void ReceiveBuffer_write ( const sMACFrame *frame,U16 length); //緩沖區增加一個數據


//#endif /* _MAC_ */