;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;-------------------------------------------------------------------------------
;
;  Header: s3c6410.inc
;
;  This header file defines only those registers required by the startup
;  code. All addresses are based off the physical addresses (PA) defined
;  in s3c6410_base_reg.h (s3c6410_base_reg.inc).
;
;-------------------------------------------------------------------------------

;-------------------------------------------------
; CPU Revision Definition ( S3C6410 Has EVT0, EVT1
;-------------------------------------------------
EVT0        EQU    (36410100)
EVT1        EQU    (36410101)

;-------------------------------------------------
; System Clock Definition
;-------------------------------------------------

CLK_66_5MHZ   EQU    66500000
CLK_133MHZ    EQU    133000000
CLK_150MHZ    EQU    150000000
CLK_200MHZ    EQU    200000000
CLK_266MHZ    EQU    266000000
CLK_300MHZ    EQU    300000000
CLK_400MHZ    EQU    400000000
CLK_450MHZ    EQU    450000000
CLK_532MHZ    EQU    532000000
CLK_600MHZ    EQU    600000000
CLK_666MHZ    EQU    666000000        ; Sync
CLK_667MHZ    EQU    667000000        ; ASync
CLK_798MHZ    EQU    798000000        ; Sync
CLK_800MHZ    EQU    800000000        ; ASync
CLK_900MHZ    EQU    900000000
CLK_1332MHZ   EQU    1332000000

ECLK_96MHZ    EQU    96000000
ECLK_84MHZ    EQU    84666667    ; for IIS 44.1 KHz
ECLK_92MHZ    EQU    92160000    ; for IIS 48 KHz

    GBLA    CPU_REVISION
    GBLA    TARGET_ARM_CLK
    GBLA    S3C6410_ECLK
    GBLL    CHANGE_PLL_CLKDIV_ON_EBOOT
    GBLL    CHANGE_PLL_CLKDIV_ON_KERNEL
    GBLL    CLEAR_DRAM_ON_EBOOT
    GBLL    CLEAR_DRAM_ON_KERNEL

CHANGE_PLL_CLKDIV_ON_EBOOT  SETL    {TRUE}
CHANGE_PLL_CLKDIV_ON_KERNEL SETL    {TRUE}
CLEAR_DRAM_ON_EBOOT         SETL    {FALSE}
CLEAR_DRAM_ON_KERNEL        SETL    {FALSE}


;------------------------------------------------------------------------------
; Define: SYNCMODE
;
; SYNCMODE used to set cpu operation mode to syncronous mode or asyncronous mode
;------------------------------------------------------------------------------

    GBLL    SYNCMODE

SYNCMODE            SETL    {TRUE}

;-------------------------------------------------
; Change CPU Revision (S3C6410 HAS EVT0, EVT1)
;-------------------------------------------------
CPU_REVISION    SETA    EVT1
;-------------------------------------------------

;-------------------------------------------------
; Change TARGET_ARM_CLK definition for StartUp code
;-------------------------------------------------
;TARGET_ARM_CLK    SETA    CLK_66_5MHZ        ; Sync 66.5:66.5:66.5
;TARGET_ARM_CLK    SETA    CLK_133MHZ        ; Sync 133:133:66.5
;TARGET_ARM_CLK    SETA    CLK_266MHZ        ; Sync 266:133:66.5
;TARGET_ARM_CLK    SETA    CLK_400MHZ        ; Sync 400:100:50
;TARGET_ARM_CLK    SETA    CLK_450MHZ        ; Sync 450:150:65
TARGET_ARM_CLK    SETA    CLK_532MHZ        ; Sync 532:133:66.5
;TARGET_ARM_CLK    SETA    CLK_600MHZ        ; Sync 600:150:75
;TARGET_ARM_CLK    SETA    CLK_666MHZ        ; Sync 666:133.2:66.5
;TARGET_ARM_CLK    SETA    CLK_798MHZ        ; Sync 798:133:66.5
;TARGET_ARM_CLK    SETA    CLK_800MHZ        ; Sync 800:133.33:66.66
;TARGET_ARM_CLK    SETA    CLK_900MHZ        ; Sync 900:150:75

FIN        EQU    12000000
;-------------------------------------------------

; Include the base register definitions
; Fout = MDIV*Fin/(PDIV*2^SDIV)
; Fvco = MDIV*Fin/PDIV

    INCLUDE s3c6410_base_regs.inc

;-------------------------------------------------
; Change S3C6410_ECLK definition for EPLL Fout
;-------------------------------------------------
;S3C6410_ECLK    SETA    ECLK_96MHZ
S3C6410_ECLK    SETA    ECLK_84MHZ
;S3C6410_ECLK    SETA    ECLK_92MHZ
;-------------------------------------------------

;-------------------------------------------------
; Set Clock Source : MPLL, APLL
;-------------------------------------------------
; MPLL Setting
    ; 400:100:25 (Asyncronous Mode)
    [ (TARGET_ARM_CLK = CLK_400MHZ)
;Fvco=800MHz, Fout=200MHz
MPLL_MVAL    EQU    (400)
MPLL_PVAL    EQU    (6)
MPLL_SVAL    EQU    (2)
    |
    ; Other Clock use 266Mhz for mDDR in Asynchronous mode
;Fvco=1064MHz, Fout=266MHz
MPLL_MVAL    EQU    (266)
MPLL_PVAL    EQU    (3)
MPLL_SVAL    EQU    (2)
    ]
MPLL_CLK    EQU     (((FIN>>MPLL_SVAL)/MPLL_PVAL)*MPLL_MVAL)    ; MPLL Clock

; APLL Setting
    [ (TARGET_ARM_CLK = CLK_400MHZ)
;Fvco=800MHz, Fout=400MHz
APLL_MVAL    EQU    (400)
APLL_PVAL    EQU    (6)
APLL_SVAL    EQU    (1)
    ]
    [ (TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ):LOR:(TARGET_ARM_CLK = CLK_133MHZ):LOR:(TARGET_ARM_CLK = CLK_66_5MHZ)
;Fvco=1064MHz, Fout=532MHz
APLL_MVAL    EQU    (266)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (1)
    ]
    [ (TARGET_ARM_CLK = CLK_600MHZ):LAND:(SYNCMODE)
;Fvco=1200MHz, Fout=600MHz
APLL_MVAL    EQU    (300)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (1)
    ]
    [ (TARGET_ARM_CLK = CLK_666MHZ)
        [ (SYNCMODE):LAND:(CPU_REVISION = EVT1)
;Fvco=1332MHz, Fout=1332MHz
APLL_MVAL    EQU    (333)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (0)
        |
;Fvco=1332MHz, Fout=666MHz
APLL_MVAL    EQU    (333)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (1)
        ]
    ]
    [ (TARGET_ARM_CLK = CLK_798MHZ):LAND:(SYNCMODE)
;Fvco=1596MHz, Fout=798MHz
APLL_MVAL    EQU    (399)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (1)
    ]
    [ (TARGET_ARM_CLK = CLK_800MHZ)
;Fvco=1600MHz, Fout=800MHz
APLL_MVAL    EQU    (400)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (1)
    ]
    [ ((TARGET_ARM_CLK = CLK_900MHZ):LAND:(SYNCMODE)):LOR:(TARGET_ARM_CLK = CLK_450MHZ)
;Fvco=900MHz, Fout=900MHz
APLL_MVAL    EQU    (225)
APLL_PVAL    EQU    (3)
APLL_SVAL    EQU    (0)
    ]
APLL_CLK        EQU    (((FIN>>APLL_SVAL)/APLL_PVAL)*APLL_MVAL)    ; APLL Clock

;-------------------------------------------------
; Set Clock Dividers
;-------------------------------------------------

MPLL_DIV    EQU    (2-1)    ; DOUT_MPLL = MPLL_Fout/2

    [(TARGET_ARM_CLK = CLK_450MHZ):LOR:(TARGET_ARM_CLK = CLK_666MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ)
APLL_DIV    EQU    (2-1)    ; ARM_CLK = APLL_CLK/2
    |
    [(TARGET_ARM_CLK = CLK_133MHZ)
APLL_DIV    EQU    (4-1)    ; ARM_CLK = APLL_CLK/4
    |
    [(TARGET_ARM_CLK = CLK_66_5MHZ)
APLL_DIV    EQU    (8-1)    ; ARM_CLK = APLL_CLK/8
    |
APLL_DIV    EQU    (1-1)    ; ARM_CLK = APLL_CLK
    ]
    ]
    ]


    [ (SYNCMODE)   ; Use APLL as Memory Clock Source
        [ (TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_600MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ):LOR:(TARGET_ARM_CLK = CLK_133MHZ)
; ARM:AHB:APB = 4:2:1, HCLKx2 = APLL_CLK/2
HCLKx2_DIV  EQU    (2-1)    ; HCLKx2 = APLL_CLK/2
        ]
        [ (TARGET_ARM_CLK = CLK_666MHZ):LAND:(CPU_REVISION = EVT1)     ; This setting requires enabling MISC_CON[19]
HCLKx2_DIV  EQU    (5-1)    ; HCLKx2 = APLL_CLK/5 = 266.4MHz(Hard wired-PreDivider on EVT1)
        ]
        [ (TARGET_ARM_CLK = CLK_798MHZ):LOR:(TARGET_ARM_CLK = CLK_900MHZ):LOR:(TARGET_ARM_CLK = CLK_450MHZ):LOR:(TARGET_ARM_CLK = CLK_800MHZ)
; ARM:AHB:APB = 12:2:1, HCLKx2 = APLL_CLK/3
HCLKx2_DIV  EQU    (3-1)    ; HCLKx2 = APLL_CLK/3
        ]
        [ (TARGET_ARM_CLK = CLK_66_5MHZ)
HCLKx2_DIV  EQU    (4-1)    ; HCLKx2 = APLL_CLK/4
        ]
    | ; Use MPLL as Memory Clock Source
        [ (TARGET_ARM_CLK = CLK_400MHZ):LOR:(TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_666MHZ)
; ARM:AHB:APB = 4:(2:1), HCLKx2 = MPLL
HCLKx2_DIV  EQU    (1-1)    ; HCLKx2 = MPLL_CLK
        ]
    ] ; (SYNCMODE)



HCLK_DIV    EQU    (2-1)    ; AHB_CLK = HCLKx2/2
    [ (TARGET_ARM_CLK = CLK_66_5MHZ)
PCLK_DIV    EQU    (2-1)    ; PCLK = HCLKx2/2
    |
PCLK_DIV    EQU    (4-1)    ; PCLK = HCLKx2/4
    ]

ARM_CLK    EQU    (APLL_CLK/(APLL_DIV+1))

    [ (SYNCMODE)
HCLK    EQU    (APLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1))
    |
HCLK    EQU    (MPLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1))
    ]

; For 532:133:66.5
; Set most Stable Clock as Stratup Clock
;Fvco=1064MHz, Fout=532MHz
Startup_APLL_MVAL    EQU    (266)
Startup_APLL_PVAL    EQU    (3)
Startup_APLL_SVAL    EQU    (1)
Startup_APLL_CLK     EQU    (((FIN>>Startup_APLL_SVAL)/Startup_APLL_PVAL)*Startup_APLL_MVAL)    ; APLL Clock

Startup_APLL_DIV    EQU    (1-1)    ; ARM_CLK = APLL_CLK
Startup_HCLKx2_DIV  EQU    (2-1)    ; HCLKx2 = APLL_CLK/2
Startup_HCLK_DIV    EQU    (2-1)    ; AHB_CLK = HCLKx2/2
Startup_PCLK_DIV    EQU    (4-1)    ; PCLK = HCLKx2/4
Startup_ARM_CLK    EQU    (Startup_APLL_CLK/(Startup_APLL_DIV+1))


    ; EPLL Fout 96 MHz
    [ S3C6410_ECLK = ECLK_96MHZ

;Fout=96MHz
EPLL_MVAL    EQU    (32)
EPLL_PVAL    EQU    (1)
EPLL_SVAL    EQU    (2)
EPLL_KVAL    EQU    (0)

      ]    ; 96 MHz

    ; EPLL Fout 84.666667 MHz
    [ S3C6410_ECLK = ECLK_84MHZ

;Fout=84.67MHz
EPLL_MVAL    EQU    (254)
EPLL_PVAL    EQU    (9)
EPLL_SVAL    EQU    (2)
EPLL_KVAL    EQU    (0)

      ]    ; 84.666667 MHz

    ; EPLL Fout 92,160,000 Hz
    [ S3C6410_ECLK = ECLK_92MHZ