?? usb.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
#ifndef _USB_H_
#define _USB_H_
#include "image_cfg.h"
#if 0
#define DBGUSB(x) EdbgOutputDebugString(x)
#else
#define DBGUSB(x)
#endif
#define DMABUFFER (EBOOT_USB_BUFFER_CA_START) // Actually this buffer is not for DMA, Just read/write with ARM
#define USBOTG_LINK_BASE (0xB1800000) //(0x7C000000) -> 0x91800000
#define USBOTG_PHY_BASE (0xB1900000) //(0x7C100000) -> 0x91900000
// IRQ Exception Handler Address
#define pISR (*(volatile unsigned *)(DRAM_BASE_PA_START+0x18)) // Virtual Address 0x0 is mapped to 0x50000000, ISR Address is VA 0x18
#define Outp32(addr, data) (*(volatile UINT32 *)(addr) = (data))
#define Outp16(addr, data) (*(volatile UINT16 *)(addr) = (data))
#define Outp8(addr, data) (*(volatile UINT8 *)(addr) = (data))
#define Inp32(addr, data) (data = (*(volatile UINT32 *)(addr)))
#define Inp16(addr, data) (data = (*(volatile UINT16 *)(addr)))
#define Inp8(addr, data) (data = (*(volatile UINT16 *)(addr)))
#define Input32(addr) (*(volatile UINT32 *)(addr))
// start // from OTG_MON/def.h
typedef BOOL bool;
#define false FALSE
#define true TRUE
// end // from OTG_MON/def.h
// start // from OTG_MON/otg_dev.h
//=====================================================================================
//
#define CONTROL_EP (0)
#define BULK_IN_EP (1)
#define BULK_OUT_EP (2)
#define FULL_SPEED_CONTROL_PKT_SIZE (8)
#define FULL_SPEED_BULK_PKT_SIZE (64)
#define HIGH_SPEED_CONTROL_PKT_SIZE (64)
#define HIGH_SPEED_BULK_PKT_SIZE (512)
#define RX_FIFO_SIZE (0x800)
#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
#define NPTX_FIFO_SIZE (0x800)
#define PTX_FIFO_SIZE (512)
// string descriptor
#define LANGID_US_L (0x09)
#define LANGID_US_H (0x04)
typedef enum
{
USB_CPU, USB_DMA
} USB_OPMODE;
typedef enum
{
USB_HIGH, USB_FULL, USB_LOW
} USB_SPEED;
typedef enum
{
EP_TYPE_CONTROL, EP_TYPE_ISOCHRONOUS, EP_TYPE_BULK, EP_TYPE_INTERRUPT
}EP_TYPE;
typedef struct
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bcdUSBL;
UINT8 bcdUSBH;
UINT8 bDeviceClass;
UINT8 bDeviceSubClass;
UINT8 bDeviceProtocol;
UINT8 bMaxPacketSize0;
UINT8 idVendorL;
UINT8 idVendorH;
UINT8 idProductL;
UINT8 idProductH;
UINT8 bcdDeviceL;
UINT8 bcdDeviceH;
UINT8 iManufacturer;
UINT8 iProduct;
UINT8 iSerialNumber;
UINT8 bNumConfigurations;
} USB_DEVICE_DESCRIPTOR;
typedef struct
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 wTotalLengthL;
UINT8 wTotalLengthH;
UINT8 bNumInterfaces;
UINT8 bConfigurationValue;
UINT8 iConfiguration;
UINT8 bmAttributes;
UINT8 maxPower;
} USB_CONFIGURATION_DESCRIPTOR;
typedef struct
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bInterfaceNumber;
UINT8 bAlternateSetting;
UINT8 bNumEndpoints;
UINT8 bInterfaceClass;
UINT8 bInterfaceSubClass;
UINT8 bInterfaceProtocol;
UINT8 iInterface;
} USB_INTERFACE_DESCRIPTOR;
typedef struct
{
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bEndpointAddress;
UINT8 bmAttributes;
UINT8 wMaxPacketSizeL;
UINT8 wMaxPacketSizeH;
UINT8 bInterval;
} USB_ENDPOINT_DESCRIPTOR;
typedef struct
{
USB_DEVICE_DESCRIPTOR oDescDevice;
USB_CONFIGURATION_DESCRIPTOR oDescConfig;
USB_INTERFACE_DESCRIPTOR oDescInterface;
USB_ENDPOINT_DESCRIPTOR oDescEndpt1;
USB_ENDPOINT_DESCRIPTOR oDescEndpt2;
} USB_DESCRIPTORS;
typedef struct
{
UINT8 bmRequestType;
UINT8 bRequest;
UINT8 wValue_L;
UINT8 wValue_H;
UINT8 wIndex_L;
UINT8 wIndex_H;
UINT8 wLength_L;
UINT8 wLength_H;
} DEVICE_REQUEST;
typedef struct
{
USB_DESCRIPTORS m_oDesc;
DEVICE_REQUEST m_oDeviceRequest;
UINT32 m_uEp0State;
UINT32 m_uEp0SubState;
USB_OPMODE m_eOpMode;
USB_SPEED m_eSpeed;
UINT32 m_uControlEPMaxPktSize;
UINT32 m_uBulkInEPMaxPktSize;
UINT32 m_uBulkOutEPMaxPktSize;
UINT32 m_uDownloadAddress;
UINT32 m_uDownloadFileSize;
UINT32 m_uUploadAddr;
UINT32 m_uUploadSize;
UINT8* m_pDownPt;
UINT8* m_pUpPt;
UINT32 m_uIsUsbOtgSetConfiguration;
} OTGDEV;
typedef struct
{
UINT8 ConfigurationValue;
} USB_CONFIGURATION_SET;
typedef struct
{
UINT8 Device;
UINT8 Interface;
UINT8 Endpoint0;
UINT8 Endpoint1;
UINT8 Endpoint2;
} USB_GET_STATUS;
typedef struct
{
UINT8 AlternateSetting;
} USB_INTERFACE_GET;
//=====================================================================================
// prototypes of API functions
void OTGDEV_InitOtg(USB_SPEED eSpeed);
void OTGDEV_HandleEvent(void);
void OTGDEV_HandleEvent_EP0(void);
void OTGDEV_TransferEp0(void);
void OTGDEV_HandleEvent_BulkIn(void);
void OTGDEV_HandleEvent_BulkOut(UINT32 fifoCntByte);
//-------------------------------------------------------------------------------------
// prototypes of sub functions
void OTGDEV_InitPhyCon(void);
void OTGDEV_SoftResetCore(void);
void OTGDEV_WaitCableInsertion(void);
void OTGDEV_InitCore(void);
void OTGDEV_CheckCurrentMode(UINT8 *pucMode);
void OTGDEV_SetSoftDisconnect(void);
void OTGDEV_ClearSoftDisconnect(void);
void OTGDEV_InitDevice(void);
void OTGDEV_SetAllOutEpNak(void);
void OTGDEV_ClearAllOutEpNak(void);
void OTGDEV_SetMaxPktSizes(USB_SPEED eSpeed);
void OTGDEV_SetEndpoint(void);
void OTGDEV_SetDescriptorTable(void);
void OTGDEV_CheckEnumeratedSpeed(USB_SPEED *eSpeed);
void OTGDEV_SetInEpXferSize(EP_TYPE eType, UINT32 uPktCnt, UINT32 uXferSize);
void OTGDEV_SetOutEpXferSize(EP_TYPE eType, UINT32 uPktCnt, UINT32 uXferSize);
void OTGDEV_WrPktEp0(UINT8 *buf, int num);
void OTGDEV_PrintEp0Pkt(UINT8 *pt, UINT8 count);
void OTGDEV_WrPktBulkInEp(UINT8 *buf, int num);
void OTGDEV_RdPktBulkOutEp(UINT8 *buf, int num);
//=====================================================================================
// prototypes of API functions
BOOL OTGDEV_IsUsbOtgSetConfiguration(void);
void OTGDEV_SetOpMode(USB_OPMODE eMode);
void OTGDEV_VerifyChecksum(void);
// end // from OTG_MON/otg_dev.h
// start // from otg_dev.c
//==========================
// OTG LINK CORE REGISTERS
//==========================
enum USBOTG_REGS
{
//==============================================================================================
// Core Global Registers
GOTGCTL = (USBOTG_LINK_BASE + 0x000), // OTG Control & Status
GOTGINT = (USBOTG_LINK_BASE + 0x004), // OTG Interrupt
GAHBCFG = (USBOTG_LINK_BASE + 0x008), // Core AHB Configuration
GUSBCFG = (USBOTG_LINK_BASE + 0x00C), // Core USB Configuration
GRSTCTL = (USBOTG_LINK_BASE + 0x010), // Core Reset
GINTSTS = (USBOTG_LINK_BASE + 0x014), // Core Interrupt
GINTMSK = (USBOTG_LINK_BASE + 0x018), // Core Interrupt Mask
GRXSTSR = (USBOTG_LINK_BASE + 0x01C), // Receive Status Debug Read/Status Read
GRXSTSP = (USBOTG_LINK_BASE + 0x020), // Receive Status Debug Pop/Status Pop
GRXFSIZ = (USBOTG_LINK_BASE + 0x024), // Receive FIFO Size
GNPTXFSIZ = (USBOTG_LINK_BASE + 0x028), // Non-Periodic Transmit FIFO Size
GNPTXSTS = (USBOTG_LINK_BASE + 0x02C), // Non-Periodic Transmit FIFO/Queue Status
HPTXFSIZ = (USBOTG_LINK_BASE + 0x100), // Host Periodic Transmit FIFO Size
DPTXFSIZ1 = (USBOTG_LINK_BASE + 0x104), // Device Periodic Transmit FIFO-1 Size
DPTXFSIZ2 = (USBOTG_LINK_BASE + 0x108), // Device Periodic Transmit FIFO-2 Size
DPTXFSIZ3 = (USBOTG_LINK_BASE + 0x10C), // Device Periodic Transmit FIFO-3 Size
DPTXFSIZ4 = (USBOTG_LINK_BASE + 0x110), // Device Periodic Transmit FIFO-4 Size
DPTXFSIZ5 = (USBOTG_LINK_BASE + 0x114), // Device Periodic Transmit FIFO-5 Size
DPTXFSIZ6 = (USBOTG_LINK_BASE + 0x118), // Device Periodic Transmit FIFO-6 Size
DPTXFSIZ7 = (USBOTG_LINK_BASE + 0x11C), // Device Periodic Transmit FIFO-7 Size
DPTXFSIZ8 = (USBOTG_LINK_BASE + 0x120), // Device Periodic Transmit FIFO-8 Size
DPTXFSIZ9 = (USBOTG_LINK_BASE + 0x124), // Device Periodic Transmit FIFO-9 Size
DPTXFSIZ10 = (USBOTG_LINK_BASE + 0x128), // Device Periodic Transmit FIFO-10 Size
DPTXFSIZ11 = (USBOTG_LINK_BASE + 0x12C), // Device Periodic Transmit FIFO-11 Size
DPTXFSIZ12 = (USBOTG_LINK_BASE + 0x130), // Device Periodic Transmit FIFO-12 Size
DPTXFSIZ13 = (USBOTG_LINK_BASE + 0x134), // Device Periodic Transmit FIFO-13 Size
DPTXFSIZ14 = (USBOTG_LINK_BASE + 0x138), // Device Periodic Transmit FIFO-14 Size
DPTXFSIZ15 = (USBOTG_LINK_BASE + 0x13C), // Device Periodic Transmit FIFO-15 Size
//==============================================================================================
// Host Mode Registers
//------------------------------------------------
// Host Global Registers
HCFG = (USBOTG_LINK_BASE + 0x400), // Host Configuration
HFIR = (USBOTG_LINK_BASE + 0x404), // Host Frame Interval
HFNUM = (USBOTG_LINK_BASE + 0x408), // Host Frame Number/Frame Time Remaining
HPTXSTS = (USBOTG_LINK_BASE + 0x410), // Host Periodic Transmit FIFO/Queue Status
HAINT = (USBOTG_LINK_BASE + 0x414), // Host All Channels Interrupt
HAINTMSK = (USBOTG_LINK_BASE + 0x418), // Host All Channels Interrupt Mask
//------------------------------------------------
// Host Port Control & Status Registers
HPRT = (USBOTG_LINK_BASE + 0x440), // Host Port Control & Status
//------------------------------------------------
// Host Channel-Specific Registers
HCCHAR0 = (USBOTG_LINK_BASE + 0x500), // Host Channel-0 Characteristics
HCSPLT0 = (USBOTG_LINK_BASE + 0x504), // Host Channel-0 Split Control
HCINT0 = (USBOTG_LINK_BASE + 0x508), // Host Channel-0 Interrupt
HCINTMSK0 = (USBOTG_LINK_BASE + 0x50C), // Host Channel-0 Interrupt Mask
HCTSIZ0 = (USBOTG_LINK_BASE + 0x510), // Host Channel-0 Transfer Size
HCDMA0 = (USBOTG_LINK_BASE + 0x514), // Host Channel-0 DMA Address
//==============================================================================================
// Device Mode Registers
//------------------------------------------------
// Device Global Registers
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