//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
// Copyright (c) Samsung Electronics. Co. LTD. All rights reserved.

/*++

THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:

    fmd.cpp

Abstract:

    This module implements main functions of FMD common PDD

Functions:

    FMD_Init,  

Notes:

--*/

#include "precomp.h"

volatile S3C6410_NAND_REG *g_pNFConReg = NULL;
volatile S3C6410_SYSCON_REG *g_pSysConReg = NULL;

// This FMD library can be included into StorageDeviceDriver and EBOOT
// There are different debugzones
extern DBGPARAM dpCurSettings;

BOOL g_bNeedExtAddr;
NANDDeviceInfo stDeviceInfo;
NANDDeviceInfo GetNandInfo(void) { return stDeviceInfo; }

/*
    @func   DWORD | ReadFlashID | Reads the flash manufacturer and device codes.
    @rdesc  Manufacturer and device codes.
    @comm
    @xref
*/
static DWORD ReadFlashID(void)
{
    BYTE Mfg, Dev;
    int i;

    NF_nFCE_L();                // Deselect the flash chip.
    NF_CMD(CMD_READID);        // Send flash ID read command.

    NF_ADDR(0);

    for (i=0; i<NAND_READ_TIMEOUT; i++)
    {
        Mfg    = NF_RDDATA_BYTE();
        if (Mfg == NAND_MID_SAMSUNG || Mfg == NAND_MID_TOSHIBA) break;
    }

    Dev    = NF_RDDATA_BYTE();

    NF_nFCE_H();

    return ((DWORD)MAKEWORD(Dev, Mfg));
}

/*
    @func   PVOID | FMD_Init | Initializes the Smart Media NAND flash controller.
    @rdesc  Pointer to S3C6410 NAND controller registers.
    @comm
    @xref
*/
PVOID FMD_Init(LPCTSTR lpActiveReg, PPCI_REG_INFO pRegIn, PPCI_REG_INFO pRegOut)
{
    volatile DWORD nNandID;
    UINT8 nMID, nDID;
    UINT32 nCnt;
    BOOL bNandExt = FALSE;
    UINT32 nTotPages;

    RETAILMSG(FMD_ZONE_FUNCTION, (TEXT("[FMD] ++FMD_Init()\r\n")));
    PHYSICAL_ADDRESS    ioPhysicalBase ={0,0};

    if (pRegIn && pRegIn->MemBase.Num && pRegIn->MemBase.Reg[0])
    {
        g_pNFConReg = (S3C6410_NAND_REG *)(pRegIn->MemBase.Reg[0]);
    }
    else
    {
        ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_NFCON;
        g_pNFConReg = (S3C6410_NAND_REG *)MmMapIoSpace(ioPhysicalBase, sizeof(S3C6410_NAND_REG), FALSE);
        if (g_pNFConReg == NULL)
        {
            RETAILMSG(FMD_ZONE_ERROR, (TEXT("Error: Io Mapping failed for NFCON Register\n")));
        }
    }

    if (pRegIn && pRegIn->MemBase.Num==2 && pRegIn->MemBase.Reg[1])
    {
        g_pSysConReg = (S3C6410_SYSCON_REG *)(pRegIn->MemBase.Reg[1]);
    }
    else
    {
        ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_SYSCON;
        g_pSysConReg = (S3C6410_SYSCON_REG *)MmMapIoSpace(ioPhysicalBase, sizeof(S3C6410_SYSCON_REG), FALSE);
        if (g_pSysConReg == NULL)
        {
            RETAILMSG(FMD_ZONE_ERROR, (TEXT("Error: Io Mapping failed for SYSCON Register\n")));
        }
    }
    
    // Configure BUS Width and Chip Select for NAND Flash
    CLEARBIT32(g_pSysConReg->MEM_SYS_CFG, BIT_ROMBUS_WIDTH);   // NAND Flash BUS Width -> 8 bit 
    // Select NFCON CS0 as Xm0CSn[2]
    g_pSysConReg->MEM_SYS_CFG &= ~(0x1<<1);

    Init_NandController();
    
    nNandID = ReadFlashID();

    nMID = HIBYTE(nNandID);
    nDID = LOBYTE(nNandID);

    RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD:INF] FMD_Init() : Read ID = 0x%08x, MID:0x%02x, DID:0x%02x\n\r"), nNandID, nMID, nDID));

    // Search Nand ID Table
    for (nCnt = 0; astNandSpec[nCnt].nMID != 0; nCnt++)
    {
        if (nDID == astNandSpec[nCnt].nDID)
        {
            bNandExt = TRUE;
            break;
        }
    }

    if (!bNandExt)
    {
        RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD:ERR] FMD_Init() : Unknown ID = 0x%08x\n\r"), nNandID));
        return NULL;
    }

    NUM_OF_BLOCKS = astNandSpec[nCnt].nNumOfBlks;
    PAGES_PER_BLOCK = astNandSpec[nCnt].nPgsPerBlk;
    SECTORS_PER_PAGE = astNandSpec[nCnt].nSctsPerPg;

    nTotPages = NUM_OF_BLOCKS * PAGES_PER_BLOCK;
    if(((nTotPages-1)>>16) != 0)
    {
        g_bNeedExtAddr = TRUE;
    }
    else
    {
        g_bNeedExtAddr = FALSE;
    }

    RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD] FMD_Init() : NUM_OF_BLOCKS = %d\n\r"), NUM_OF_BLOCKS));
    RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD] FMD_Init() : PAGES_PER_BLOCK = %d\n\r"), PAGES_PER_BLOCK));
    RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD] FMD_Init() : SECTORS_PER_PAGE = %d\n\r"), SECTORS_PER_PAGE));
    RETAILMSG(FMD_ZONE_STATUS, (TEXT("[FMD] FMD_Init() : Addr Cycle = %d\n\r"), g_bNeedExtAddr ? 5 : 4));    

    RETAILMSG(FMD_ZONE_FUNCTION, (TEXT("[FMD] --FMD_Init()\r\n")));

    return((PVOID)g_pNFConReg);
}


/*
    @func   BOOL | FMD_ReadSector | Reads the specified sector(s) from NAND flash.
    @rdesc  TRUE = Success, FALSE = Failure.
    @comm
    @xref
*/
BOOL FMD_ReadSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff, DWORD dwNumSectors)
{
    BOOL bRet;

    RETAILMSG(FMD_ZONE_READ, (TEXT("[FMD] ++FMD_ReadSector(0x%08x) \r\n"), startSectorAddr));

    if ( IS_LB )
    {
        bRet = FMD_LB_ReadSector(startSectorAddr, pSectorBuff, pSectorInfoBuff, dwNumSectors);
    }
    else
    {
        bRet = FMD_SB_ReadSector(startSectorAddr, pSectorBuff, pSectorInfoBuff, dwNumSectors);
    }

    RETAILMSG(FMD_ZONE_READ, (TEXT("[FMD] --FMD_ReadSector()\r\n")));

    return bRet;
}


/*
    @func   BOOL | FMD_EraseBlock | Erases the specified flash block.
    @rdesc  TRUE = Success, FALSE = Failure.
    @comm
    @xref
*/
BOOL FMD_EraseBlock(BLOCK_ID blockID)
{
    BOOL    bRet = TRUE;

    RETAILMSG(FMD_ZONE_ERASE, (TEXT("[FMD] ++FMD_EraseBlock(0x%08x) \r\n"), blockID));

    if ( IS_LB )
    {
        bRet = FMD_LB_EraseBlock(blockID);
    }
    else
    {
        bRet = FMD_SB_EraseBlock(blockID);
    }

    RETAILMSG(FMD_ZONE_ERASE, (TEXT("[FMD] --FMD_EraseBlock()\r\n")));

    return bRet;
}


/*
    @func   BOOL | FMD_WriteSector | Writes the specified data to the specified NAND flash sector/page.
    @rdesc  TRUE = Success, FALSE = Failure.
    @comm
    @xref
*/
BOOL FMD_WriteSector(SECTOR_ADDR startSectorAddr, LPBYTE pSectorBuff, PSectorInfo pSectorInfoBuff, DWORD dwNumSectors)
{
    BOOL    bRet = TRUE;

    RETAILMSG(FMD_ZONE_WRITE, (TEXT("[FMD] ++FMD_WriteSector(0x%08x) \r\n"), startSectorAddr));

    if ( IS_LB )
    {
        bRet = FMD_LB_WriteSector(startSectorAddr, pSectorBuff, pSectorInfoBuff, dwNumSectors);
    }
    else
    {
        bRet = FMD_SB_WriteSector(startSectorAddr, pSectorBuff, pSectorInfoBuff, dwNumSectors);
    }

    RETAILMSG(FMD_ZONE_WRITE, (TEXT("[FMD] --FMD_WriteSector()\r\n")));

    return bRet;
}


VOID FMD_PowerUp(VOID)
{
    RETAILMSG(FMD_ZONE_FUNCTION, (TEXT("[FMD] FMD_PowerUp() \r\n")));
    // Set up initial flash controller configuration.
    Init_NandController();
}


VOID FMD_PowerDown(VOID)
{
    DEBUGMSG(FMD_ZONE_FUNCTION, (TEXT("[FMD] FMD_PowerDown() \r\n")));
    // Using PMIC Power off is preferable for saving the power of NANDFlash attached to PMIC
    // See the board's Electrical Circuit
}


BOOL FMD_OEMIoControl(DWORD dwIoControlCode, PBYTE pInBuf, DWORD nInBufSize, PBYTE pOutBuf, DWORD nOutBufSize, PDWORD pBytesReturned)
{
    switch(dwIoControlCode)
    {
        case IOCTL_FMD_GET_INTERFACE:
        {
            RETAILMSG(FMD_ZONE_FUNCTION, (TEXT("[FMD] FMD_OEMIoControl() : IOCTL_FMD_GET_INTERFACE\r\n")));

            if (!pOutBuf || nOutBufSize < sizeof(FMDInterface))
            {
                DEBUGMSG(FMD_ZONE_ERROR, (TEXT("FMD_OEMIoControl: IOCTL_FMD_GET_INTERFACE bad parameter(s).\r\n")));
                return(FALSE);
            }

            PFMDInterface pInterface = (PFMDInterface)pOutBuf;