//
// Copyright (c) Samsung Electronics. Co. LTD.  All rights reserved.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

*/


#ifndef __SAMSUNG_SYSLSI_APDEV_MFC_H__
#define __SAMSUNG_SYSLSI_APDEV_MFC_H__

#ifdef __cplusplus
extern "C" {
#endif



//SDRAM buffer control options 
#define STREAM_ENDIAN_LITTLE              (0<<0)
#define STREAM_ENDIAN_BIG                 (1<<0)
#define BUF_STATUS_FULL_EMPTY_CHECK_BIT   (0<<1)
#define BUF_STATUS_NO_CHECK_BIT           (1<<1)
                                          
// FRAME_BUF_CTRL (0x110)                 
#define FRAME_MEM_ENDIAN_LITTLE           (0<<0)
#define FRAME_MEM_ENDIAN_BIG              (1<<0)

/*
**    PRiSM-CX Video Codec IP's Register
**    V178
*/

/* DEC_SEQ_INIT Parameter Register */
// DEC_SEQ_OPTION (0x18c)                 
#define MP4_DBK_DISABLE                   (0<<0)
#define MP4_DBK_ENABLE                    (1<<0)
#define REORDER_DISABLE                   (0<<1)
#define REORDER_ENABLE                    (1<<1)
#define FILEPLAY_ENABLE                   (1<<2)
#define FILEPLAY_DISABLE                  (0<<2)
#define DYNBUFALLOC_ENABLE                (1<<3)
#define DYNBUFALLOC_DISABLE               (0<<3)

/* ENC_SEQ_INIT Parameter Register */
// ENC_SEQ_OPTION (0x188)
#define MB_BIT_REPORT_DISABLE             (0<<0)
#define MB_BIT_REPORT_ENABLE              (1<<0)
#define SLICE_INFO_REPORT_DISABLE         (0<<1)
#define SLICE_INFO_REPORT_ENABLE          (1<<1)
#define AUD_DISABLE                       (0<<2)
#define AUD_ENABLE                        (1<<2)
#define MB_QP_REPORT_DISABLE              (0<<3)
#define MB_QP_REPORT_ENBLE                (1<<3)
#define CONST_QP_DISABLE                  (0<<5)
#define CONST_QP_ENBLE                    (1<<5)

// ENC_SEQ_COD_STD (0x18C)
#define MPEG4_ENCODE                      0
#define H263_ENCODE                       1
#define H264_ENCODE                       2

// ENC_SEQ_MP4_PARA (0x198)
#define DATA_PART_DISABLE                 (0<<0)
#define DATA_PART_ENABLE                  (1<<0)

// ENC_SEQ_263_PARA (0x19C)
#define ANNEX_T_OFF                       (0<<0)
#define ANNEX_T_ON                        (1<<0)
#define ANNEX_K_OFF                       (0<<1)
#define ANNEX_K_ON                        (1<<1)
#define ANNEX_J_OFF                       (0<<2)
#define ANNEX_J_ON                        (1<<2)
#define ANNEX_I_OFF                       (0<<3)
#define ANNEX_I_ON                        (1<<3)

// ENC_SEQ_SLICE_MODE (0x1A4)
#define SLICE_MODE_ONE                    (0<<0)
#define SLICE_MODE_MULTIPLE               (1<<0)

// ENC_SEQ_RC_PARA (0x1AC)
#define RC_DISABLE                        (0<<0)    // RC means rate control
#define RC_ENABLE                         (1<<0)
#define SKIP_DISABLE                      (1<<31)
#define SKIP_ENABLE                       (0<<31)

// ENC_SEQ_FMO (0x1B8)
#define FMO_DISABLE                       (0<<0)
#define FMO_ENABLE                        (1<<0)

// ENC_SEQ_RC_OPTION (0x1C4)
#define USER_QP_MAX_DISABLE               (0<<0)
#define USER_QP_MAX_ENABLE                (1<<0)
#define USE_GAMMA_DISABLE                 (0<<1)
#define USE_GAMMA_ENABLE                  (1<<1)
    

typedef enum __MFC_CODEC_MODE
{
    MP4_DEC    = 0,
    MP4_ENC    = 1,
    AVC_DEC    = 2,
    AVC_ENC    = 3,
    VC1_DEC    = 4,
    H263_DEC   = 5,
    H263_ENC   = 6
} MFC_CODECMODE;

typedef enum __MFC_COMMAND
{
    SEQ_INIT         = 0x01,
    SEQ_END          = 0x02,
    PIC_RUN          = 0x03,
    SET_FRAME_BUF    = 0x04,
    ENC_HEADER       = 0x05,
    ENC_PARA_SET     = 0x06,
    DEC_PARA_SET     = 0x07,
    ENC_PARAM_CHANGE = 0x09,
    SLEEP            = 0x0A,
    WAKEUP           = 0x0B,
    GET_FW_VER       = 0x0F
} MFC_COMMAND;

typedef struct tagS3C6410_MFC_PARAM_REG_DEC_SEQ_INIT
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for rnc.dec//
    // (0x180 ~ 0x1A0)                     //
    ///////////////////////////////////////

    unsigned int DEC_SEQ_BIT_BUF_ADDR;     // 0x180,
    unsigned int DEC_SEQ_BIT_BUF_SIZE;     // 0x184,
    unsigned int DEC_SEQ_OPTION;           // 0x188,
    unsigned int DEC_SEQ_PRO_BUF;          // 0x18c,
    unsigned int DEC_SEQ_TMP_BUF_1;        // 0x190,
    unsigned int DEC_SEQ_TMP_BUF_2;        // 0x194,
    unsigned int DEC_SEQ_TMP_BUF_3;        // 0x198,
    unsigned int DEC_SEQ_TMP_BUF_4;        // 0x19c,
    unsigned int DEC_SEQ_TMP_BUF_5;        // 0x1a0,
    unsigned int DEC_SEQ_START_BYTE;       // 0x1a4

    unsigned int _reserved[6];             // 0x1b8, 0x1bc


    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1D4) //
    /////////////////////
    unsigned int RET_SEQ_SUCCESS;                // 0x1c0,
    unsigned int RET_DEC_SEQ_SRC_SIZE;           // 0x1c4,
    unsigned int RET_DEC_SEQ_SRC_FRAME_RATE;     // 0x1c8,
    unsigned int RET_DEC_SEQ_FRAME_NEED_COUNT;   // 0x1cc,
    unsigned int RET_DEC_SEQ_FRAME_DELAY;        // 0x1d0,
    unsigned int RET_DEC_SEQ_INFO;               // 0x1d4,
    unsigned int RET_DEC_SEQ_TIME_RES;           // 0x1d8,

} S3C6410_MFC_PARAM_REG_DEC_SEQ_INIT;

typedef struct tagS3C6410_MFC_PARAM_REG_ENC_SEQ_INIT
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for encdoer//
    // (0x180 ~ 0x1BC, 0x1C4 ~ 0x1DC)    //
    ///////////////////////////////////////

    unsigned int ENC_SEQ_BIT_BUF_ADDR;        // 0x180,
    unsigned int ENC_SEQ_BIT_BUF_SIZE;        // 0x184,
    unsigned int ENC_SEQ_OPTION;        // 0x188,
    unsigned int ENC_SEQ_COD_STD;        // 0x18c,
    unsigned int ENC_SEQ_SRC_SIZE;        // 0x190,
    unsigned int ENC_SEQ_SRC_F_RATE;        // 0x194,
    unsigned int ENC_SEQ_MP4_PARA;        // 0x198,
    unsigned int ENC_SEQ_263_PARA;        // 0x19c,
    unsigned int ENC_SEQ_264_PARA;        // 0x1a0,
    unsigned int ENC_SEQ_SLICE_MODE;        // 0x1a4
    unsigned int ENC_SEQ_GOP_NUM;        // 0x1a8
    unsigned int ENC_SEQ_RC_PARA;        // 0x1ac
    unsigned int ENC_SEQ_RC_BUF_SIZE;        // 0x1b0
    unsigned int ENC_SEQ_INTRA_MB;        // 0x1b4
    unsigned int ENC_SEQ_FMO;            // 0x1b8
    unsigned int ENC_SEQ_INTRA_QP;        // 0x1bc

    /////////////////////
    //  OUTPUT RETURN  //
    //     (0x1C0)     //
    /////////////////////
    unsigned int RET_ENC_SEQ_SUCCESS;        // 0x1c0

    unsigned int ENC_SEQ_RC_OPTION;        // 0x1c4
    unsigned int ENC_SEQ_RC_QP_MAX;        // 0x1c8
    float             ENC_SEQ_RC_GAMMA;        // 0x1cc

    unsigned int ENC_SEQ_TMP_BUF1;        // 0x1d0
    unsigned int ENC_SEQ_TMP_BUF2;        // 0x1d4
    unsigned int ENC_SEQ_TMP_BUF3;        // 0x1d8
    unsigned int ENC_SEQ_TMP_BUF4;        // 0x1dc
} S3C6410_MFC_PARAM_REG_ENC_SEQ_INIT;

typedef struct tagS3C6410_MFC_PARAM_REG_SET_FRAME_BUF
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for rnc.dec//
    // (0x180 ~ 0x1A0)                  //
    ///////////////////////////////////////

    unsigned int SET_FRAME_BUF_NUM;        // 0x180,
    unsigned int SET_FRAME_BUF_STRIDE;     // 0x184,

/*
    //encoder
    UINT32 ENC_SEQ_SLICE_MODE;         // 0x1a4,
    UINT32 ENC_SEQ_GOP_NUM;            // 0x1a8,
    UINT32 ENC_SEQ_RC_PARA;            // 0x1ac,
    UINT32 ENC_SEQ_RC_BUF_SIZE;        // 0x1b0,
    UINT32 ENC_SEQ_INTRA_MB;           // 0x1b4,
*/

    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1D4) //
    /////////////////////

} S3C6410_MFC_PARAM_REG_SET_FRAME_BUF;

typedef struct tagS3C6410_MFC_PARAM_REG_DEC_PIC_RUN
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for rnc.dec//
    // (0x180 ~ 0x1A0)             //
    ///////////////////////////////////////