unsigned int DEC_PIC_ROT_MODE;             // 0x180, Display frame post-rotator mode
    unsigned int DEC_PIC_ROT_ADDR_Y;           // 0x184, Post-rotated frame store Y address
    unsigned int DEC_PIC_ROT_ADDR_CB;          // 0x188, Post-rotated frame store Cb address
    unsigned int DEC_PIC_ROT_ADDR_CR;          // 0x18c, Post-rotated frame store Cr address
    unsigned int DEC_PIC_DBK_ADDR_Y;           // 0x190, Deblocked frame store Y address
    unsigned int DEC_PIC_DBK_ADDR_CB;          // 0x194, Deblocked frame store Cb address
    unsigned int DEC_PIC_DBK_ADDR_CR;          // 0x198, Deblocked frame store Cr address
    unsigned int DEC_PIC_ROT_STRIDE;           // 0x19c, Post-rotated frame stride
    unsigned int DEC_PIC_OPTION;               // 0x1a0, Decoding option
    unsigned int _reserved1[1];                // 0x1a4
    unsigned int DEC_PIC_CHUNK_SIZE;           // 0x1a8, Frame chunk size
    unsigned int DEC_PIC_BB_START;             // 0x1ac, 4-byte aligned start address of picture stream buffer
    unsigned int DEC_PIC_START_BYTE;           // 0x1b0, Start byte of valid stream data
    unsigned int DEC_PIC_MV_ADDR;              // 0x1b4, Base address for Motion Vector data
    unsigned int DEC_PIC_MBTYPE_ADDR;          // 0x1b8, Base address for MBType data

    unsigned int _reserved2[1];                // 0x1bc


    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1E0) //
    /////////////////////
    unsigned int RET_DEC_PIC_FRAME_NUM;        // 0x1c0, Decoded frame number
    unsigned int RET_DEC_PIC_IDX;              // 0x1c4, Display frame index
    unsigned int RET_DEC_PIC_ERR_MB_NUM;       // 0x1c8, Error MB number in decodec picture
    unsigned int RET_DEC_PIC_TYPE;             // 0x1cc, Decoded picture type
    unsigned int _reserved3[2];                // 0x1d0~0xd4
    unsigned int RET_DEC_PIC_SUCCESS;          // 0x1d8, Command executing result status
    unsigned int RET_DEC_PIC_CUR_IDX;          // 0x1dc, Decoded frame index
    unsigned int RET_DEC_PIC_FCODE_FWD;        // 0x1e0, FCODE value
    unsigned int RET_DEC_PIC_TRD;              // 0x1e4, TRD value
    unsigned int RET_DEC_PIC_TIME_BASE_LAST;   // 0x1e8, TIME_BASE_LAST value
    unsigned int RET_DEC_PIC_NONB_TIME_LAST;   // 0x1ec, NONB_TIME_LAST value
    unsigned int RET_DEC_PIC_BCNT;             // 0x1f0, the size of frame consumed

} S3C6410_MFC_PARAM_REG_DEC_PIC_RUN;


typedef struct tagS3C6410_MFC_PARAM_REG_ENC_PIC_RUN
{
    ////////////////////////////////////////
    // INPUT ARGUMENTS common for encoder //
    // (0x180 ~ 0x194)                    //
    ////////////////////////////////////////
    unsigned int ENC_PIC_SRC_ADDR_Y;       // 0x180
    unsigned int ENC_PIC_SRC_ADDR_CB;      // 0x184
    unsigned int ENC_PIC_SRC_ADDR_CR;      // 0x188
    unsigned int ENC_PIC_QS;               // 0x18c
    unsigned int ENC_PIC_ROT_MODE;         // 0x190
    unsigned int ENC_PIC_OPTION;           // 0x194
    unsigned int ENC_PIC_BB_START;         // 0x198
    unsigned int ENC_PIC_BB_SIZE;          // 0x19c

    unsigned int _reserved[8];             // 0x1a0, 0x1a4, 0x1a8, 0x1ac, 
                                           // 0x1b0, 0x1b4, 0x1b8, 0x1bc,

    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1CC) //
    /////////////////////
    unsigned int RET_ENC_PIC_FRAME_NUM;    // 0x1c0
    unsigned int RET_ENC_PIC_TYPE;         // 0x1c4
    unsigned int RET_ENC_PIC_IDX;          // 0x1c8
    unsigned int RET_ENC_PIC_SLICE_NUM;    // 0x1cc
    unsigned int RET_ENC_PIC_FLAG;         // 0x1d0
} S3C6410_MFC_PARAM_REG_ENC_PIC_RUN;


typedef struct tagS3C6410_MFC_PARAM_REG_ENC_PARA_SET
{
    ////////////////////////////////////////
    // INPUT ARGUMENTS common for encoder //
    // (0x180 ~ 0x194)                    //
    ////////////////////////////////////////
    unsigned int ENC_PARA_SET_TYPE;     // 0X180

    unsigned int _reserved[15];         // 0x184, 0x188, 0x18c,
                                        // 0x190, 0x194, 0x198, 0x19c,
                                        // 0x1a0, 0x1a4, 0x1a8, 0x1ac,
                                        // 0x1b0, 0x1b4, 0x1b8, 0x1bc,

    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1CC) //
    /////////////////////
    unsigned int RET_ENC_PARA_SET_SIZE;    // 0x1c0

} S3C6410_MFC_PARAM_REG_ENC_PARA_SET;


typedef struct tagS3C6410_MFC_PARAM_REG_ENC_HEADER
{
    ////////////////////////////////////////
    // INPUT ARGUMENTS common for encoder //
    // (0x180 ~ 0x194)                    //
    ////////////////////////////////////////
    unsigned int ENC_HEADER_CODE;       // 0x180
    unsigned int ENC_HEADER_BB_START;   // 0x184
    unsigned int ENC_HEADER_BB_SIZE;    // 0x188
    unsigned int ENC_HEADER_NUM;        // 0x18c

    unsigned int _reserved[12];         // 0x190, 0x194, 0x198, 0x19c,
                                        // 0x1a0, 0x1a4, 0x1a8, 0x1ac,
                                        // 0x1b0, 0x1b4, 0x1b8, 0x1bc,

    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1CC) //
    /////////////////////

} S3C6410_MFC_PARAM_REG_ENC_HEADER;



typedef struct tagS3C6410_MFC_PARAM_REG_ENC_PARAM_CHANGE
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for encoder//
    // (0x180 ~ 0x194)                     //
    ///////////////////////////////////////
    unsigned int ENC_PARAM_CHANGE_ENABLE;           // 0x180
    unsigned int ENC_PARAM_CHANGE_GOP_NUM;          // 0x184
    unsigned int ENC_PARAM_CHANGE_INTRA_QP;         // 0x188
    unsigned int ENC_PARAM_CHANGE_BITRATE;          // 0x18c
    unsigned int ENC_PARAM_CHANGE_F_RATE;           // 0x190
    unsigned int ENC_PARAM_CHANGE_INTRA_REFRESH;    // 0x194
    unsigned int ENC_PARAM_CHANGE_SLICE_MODE;       // 0x198
    unsigned int ENC_PARAM_CHANGE_HEC_MODE;         // 0x19c

    unsigned int _reserved[8];            // 0x1a0, 0x1a4, 0x1a8, 0x1ac, 
                                          // 0x1b0, 0x1b4, 0x1b8, 0x1bc,

    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1CC) //
    /////////////////////
    unsigned int RET_ENC_PARAM_CHANGE_SUCCESS;        // 0x1c0
} S3C6410_MFC_PARAM_REG_ENC_PARAM_CHANGE;


typedef struct tagS3C6410_MFC_PARAM_REG_FIRMWARE_VER
{
    ///////////////////////////////////////
    // INPUT ARGUMENTS common for rnc.dec//
    // (0x180 ~ 0x1A0)                      //
    ///////////////////////////////////////
    unsigned int _reserved[16];        // 0x180 ~ 0x1bc


    /////////////////////
    //  OUTPUT RETURN  //
    // (0x1C0 ~ 0x1D4) //
    /////////////////////
    unsigned int RET_GET_FW_VER;       // 0x1c0,

} S3C6410_MFC_PARAM_REG_FIRMWARE_VER;

typedef struct
{
    unsigned int BITS_RD_PTR;          // 0x120,
    unsigned int BITS_WR_PTR;          // 0x124,
} ST_BITSTRM_BUF_RW_ADDR;

typedef struct tagS3C6410_MFC_HOSTIF_REG
{
    unsigned int CODE_RUN;             // 0x000,
        // [0] 1=Start the bit processor, 0=Stop.
    unsigned int CODE_DN_LOAD;         // 0x004,
        // [15:0]
        // [28:16]
    unsigned int HOST_INTR;            // 0x008,
        // [0] Write '1' to this bit to request an interrupt to BIT
    unsigned int BITS_INT_CLEAR;       // 0x00c,
        // [0]
    unsigned int BITS_INT_STAT;        // 0x010,
        // [0] 1 means that BIT interrupt to the host is asserted.
    unsigned int BITS_CODE_RESET;      // 0x014,
    unsigned int BITS_CUR_PC;          // 0x018,

    unsigned int _reserved1[57];       // 0x01c ~ 0x0fc

    unsigned int CODE_BUF_ADDR;        // 0x100,
    unsigned int WORK_BUF_ADDR;        // 0x104,
    unsigned int PARA_BUF_ADDR;        // 0x108,
    unsigned int STRM_BUF_CTRL;        // 0x10c,
    unsigned int FRME_BUF_CTRL;        // 0x110,
    unsigned int DEC_FUNC_CTRL;        // 0x114, // 7th fw
    unsigned int _reserved2[1];        // 0x118
    unsigned int WORK_BUF_CTRL;        // 0x11c, // 7th fw

    ST_BITSTRM_BUF_RW_ADDR   BIT_STR_BUF_RW_ADDR[8];    // 0x120 ~ 0x15c


    unsigned int BUSY_FLAG;            // 0x160,
    unsigned int RUN_CMD;              // 0x164,
    unsigned int RUN_INDEX;            // 0x168,
    unsigned int RUN_COD_STD;          // 0x16c,
    unsigned int INT_ENABLE;           // 0x170,
    unsigned int INT_REASON;           // 0x174,

    unsigned int _reserved3[2];        // 0x178 ,0x17c

    // Union for the parameters of the MFC commands
    union {
        S3C6410_MFC_PARAM_REG_DEC_SEQ_INIT       dec_seq_init;
        S3C6410_MFC_PARAM_REG_ENC_SEQ_INIT       enc_seq_init;
        S3C6410_MFC_PARAM_REG_SET_FRAME_BUF      set_frame_buf;
        S3C6410_MFC_PARAM_REG_DEC_PIC_RUN        dec_pic_run;
        S3C6410_MFC_PARAM_REG_ENC_PIC_RUN        enc_pic_run;

        S3C6410_MFC_PARAM_REG_ENC_PARA_SET       enc_para_set;
        S3C6410_MFC_PARAM_REG_ENC_HEADER         enc_header;

        S3C6410_MFC_PARAM_REG_FIRMWARE_VER       get_fw_ver;
    } param;

} S3C6410_MFC_SFR;

// Because SW_RESET register is located apart(address 0xe00), unlike other MFC_SFR registers,
// I have excluded it in S3C6410_MFC_SFR struct and defined relative address only.
// When do virtual memory mapping in setting up memory, we have to map until this SW_RESET register.
#define S3C6410_MFC_SFR_SW_RESET_ADDR    (0x0e00)
#define S3C6410_MFC_SFR_SIZE                        (0x0e00)


#ifdef __cplusplus
}
#endif

#endif /* __SAMSUNG_SYSLSI_APDEV_MFC_H__ */