?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity rxd is generic( RX_IDLE : integer := 1; RX_SYNC : integer := 2; RX_DATA : integer := 4; RX_PARITY : integer := 8; RX_STOP : integer := 16; RX_ENDING : integer := 32; RX_DONE : integer := 64 ); port( clk : in vl_logic; rst_n : in vl_logic; clk_en : in vl_logic; data_o : out vl_logic_vector(7 downto 0); rxd_xi : in vl_logic; ctrl_i : in vl_logic_vector(2 downto 0); frame_bits_i : in vl_logic_vector(3 downto 0); stat_o : out vl_logic_vector(3 downto 0); enable : in vl_logic; debug_o : out vl_logic_vector(7 downto 0) );end rxd;
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