library verilog;use verilog.vl_types.all;entity ebi is    port(        clk             : in     vl_logic;        ebi_ad          : inout  vl_logic_vector(7 downto 0);        ebi_addr_h      : in     vl_logic_vector(7 downto 0);        ebi_wr_n        : in     vl_logic;        ebi_rd_n        : in     vl_logic;        ebi_ale         : in     vl_logic;        we              : out    vl_logic;        data_in         : in     vl_logic_vector(7 downto 0);        data_out        : out    vl_logic_vector(7 downto 0);        addr_out        : out    vl_logic_vector(15 downto 0)    );end ebi;