define_design_lib WORK -path ../work#---------------------------------------------#set library#----------------------------------------------source ./set_lib.tcl#report_lib -all > ../rpt/report_lib.rpt#-------------------------------------------------#             Synopsys Switches            #-------------------------------------------------#/*get rid of tri-state declarations and assigns*/set verilogout_no_tri trueset verilogout_equation false#/*enable if def processing*/set hdlin_enable_vpp true#/*enable inferred latch warnings*/set hdlin_check_no_latch true#/*disable skew for feedback loops*/set timing_self_loops_no_skew true#/*clock gating control*/#set power_cg_flatten true#set power_hdlc_do_not_split_cg_cells "false"#set power_preserve_rtl_hier_names true#set hdlin_no_group_register "true"#------------------------------------------------# Map Design#------------------------------------------------source ./analyze.tclelaborate hdlc_recvcurrent_design hdlc_recvlink#write -f db -h -o ../out/Filter.unmapped.hier.db#set_port_is_pad {iModeTest iClkTest inRstTest iScanIn iScanEn oScanOut iClk inRst oData oClk}#insert_padssource ./constraints.tcl#set_clock_gating_style -sequential latch#insert_clock_gatingcheck_design > ../rpt/check_design.rptwrite_script -format dctcl -output ../out/hdlc_recv.sdcuniquify#propagate_constraints -gate_clockset_fix_multiple_port_nets -all -buffer_constantscompile -map_effort medium #write -f db -h -o ../out/Filter.map.hier.db#write -f verilog -h -o ../out/Filter.map.hier.vset_fix_hold $CLK_PORTungroup -all -flattencompile -incsource ./dft.tclcompile -scan write -f db -h -o ../out/hdlc_recv.dbwrite -f verilog -h -o ../out/hdlc_recv.v#--------------------------------------------------#report#--------------------------------------------------report_clock > ../rpt/report_clock.rptreport_design > ../rpt/report_design.rptreport_constraint -all_violators > ../rpt/report_constraint.rpt#report_timing -nworst 5report_timing -path  full_clock -cap -tran -net -delay max -nworst 5 > ../rpt/max_timing.rptreport_timing -path  full_clock -cap -tran -net -delay min > ../rpt/min_timing.rptreport_area > ../rpt/report_area.rptreport_power > ../rpt/report_power.rptreport_net_fanout -threshold 50 > ../rpt/hign_fanout.rptquit