(you don't need to rely on linked dependencies). The dependency line
lists all the targets you want to build. You don't type any commands
for a symbolic target.

In the following makefile, the symbolic target "allFiles" builds both
FILE1.EXE and FILE2.EXE:

  allFiles: file1.exe file2.exe     #Note this target has no commands.
  file1.exe: file1.obj
  	bcc file1.obj
  file2.exe: file2.obj
  	bcc file2.obj


Rules for symbolic targets
- - - - - - - - - - - - - -
Observe the following rules with symbolic targets:

  o  Symbolic targets don't need a command line.

  o  Give your symbolic target a unique name; it can't be the name of a
     file in your current directory.

  o  Name symbolic targets according to the operating system rules for
     naming files.


Explicit and implicit rules
===========================
The explicit and implicit rules that instruct MAKE are generally
defined as follows:

  o  Explicit rules give MAKE instructions for specific files.

  o  Implicit rules give general instructions that MAKE follows when it
     can't find an explicit rule.

Rules follow this general format:

  Dependency line
	Commands

The dependency line is different for explicit and implicit rules, but
the commands are the same.

MAKE supports multiple rules for one target. You can add dependent
files after the first explicit rule, but only one should contain a
command line. For example:

  Target1: dependent1 dep2 dep3 dep4 dep5
  Target1: dep6 dep7 dep8
    bcc -c $**


Explicit rule syntax
--------------------
Explicit rules are instructions to MAKE that specify exact file names.
The explicit rule names one or more targets followed by one or two
colons. One colon means one rule is written for the target; two colons
mean that two or more rules are written for the target.

Explicit rules follow this syntax:

  target [target...]:[:][{path}] [dependent[s]...]
	[commands]

 o  target	The name and extension of the file to be updated
		("target" must be at the start of the line--no spaces or
		tabs are allowed). One or more targets must be
		separated by spaces or tabs. Don't use a target's name
		more than once in the target position of an explicit
		rule in a makefile.

 o  path	A list of directories, separated by semicolons and
		enclosed in braces, that points to the dependent files.

 o  dependent	The file (or files) whose date and time MAKE checks to
		see if it is newer than "target" (dependent must be
		preceded by a space). If a dependent file also appears
		in the makefile as a target, MAKE updates or creates
		the target file before using it as a dependent for
		another target.

 o  commands	Any operating system command. Multiple commands are
		allowed in a rule. Commands must be indented by at
		least one space or tab.

If the dependency or command continues on to the next line, use the
backslash (\) at the end of the line after a target or a dependent
file name. For example:

  MYSOURCE.EXE: FILE1.OBJ\
              FILE2.OBJ\
              FILE3.OBJ
     bcc file1.obj file2.obj file3.obj


Single targets with multiple rules
- - - - - - - - - - - - - - - - - -
A single target can have more than one explicit rule. You must use the
double colon (::) after the target name to tell MAKE to expect multiple
explicit rules. The following example shows how one target can have
multiple rules and commands:

  .cpp.obj:
	bcc -c -ncobj $<

  .asm.obj:
	tasm  /mx $<, asmobj\\

  mylib.lib :: f1.obj f2.obj
	echo Adding C files
	tlib mylib -+cobj\f1 -+cobj\f2

  mylib.lib :: f3.obj f4.obj
	echo Adding ASM files
	tlib mylib -+asmobj\f3 -+asmobj\f4


Implicit rule syntax
--------------------
An implicit rule starts with either a path or a period and implies a
target-dependent file relationship. Its main components are file
extensions separated by periods. The first extension belongs to the
dependent, the second to the target.

If implicit dependents are out-of-date with respect to the target or
if they don't exist, MAKE executes the commands associated with the
rule. MAKE updates explicit dependents before it updates implicit
dependents.

Implicit rules follow this basic syntax:

  [{source_dirs}].source_ext[{target_dirs}].target_ext:
     [commands]

  o  {source_dirs}	The directory of the dependent files.
			Separate multiple directories with a semicolon.

  o  .source_ext	The dependent file-name extension.

  o  {target_dirs}	The directory of the target (executable) files.
			Separate multiple directories with a semicolon.

  o  .target_ext	The target file-name extension. Macros are allowed.

  o  :			Marks the end of the dependency line.

  o  commands		Any operating system command. Multiple commands
			are allowed. Commands must be indented by one
			space or tab.

If two implicit rules match a target extension but no dependent
exists, MAKE uses the implicit rule whose dependent's extension
appears first in the .SUFFIXES list.


Explicit rules with implicit commands
- - - - - - - - - - - - - - - - - - -
A target in an explicit rule can get its command line from an implicit
rule. The following example shows an implicit rule and an explicit
rule without a command line:

  .c.obj:
     bcc -c $<     #This command uses a macro $< described later.

  myprog.obj:      #This explicit rule uses the command: bcc -c myprog.c

The implicit rule command tells MAKE to compile MYPROG.C (the macro $<
replaces the name "myprog.obj" with "myprog.c").


Commands syntax
---------------
Commands can be any operating system command, but they can also
include MAKE macros, directives, and special operators that operating
systems can't recognize (note that | can't be used in commands). Here
are some sample commands:

  cd..

  bcc -c mysource.c

  COPY *.OBJ C:\PROJECTA

  bcc -c $(SOURCE)     #Macros are explained later in the chapter.

Commands follow this general syntax:

	[prefix...] commands


Command prefixes
- - - - - - - - -
Commands in both implicit and explicit rules can have prefixes that
modify how MAKE treats the commands. The following table lists the prefixes
you can use in makefiles:

Option		Description
------		-----------
@		Don't display command while it's being executed.

-<num>		Stop processing commands in the makefile when the
		exit code returned from command exceeds <num>.
		Normally, MAKE aborts if the exit code is nonzero.
		No white space is allowed between - and <num>.

-		Continue processing commands in the makefile,
		regardless of the exit code returned by them.

&		Expand either the macro $**, which represents all
		dependent files, or the macro $?, which represents
		all dependent files stamped later than the target.
		Execute the command once for each dependent file
		in the expanded macro.


Using @
- - - -
The following command uses the modifier @, which prevents the command
from displaying onscreen when MAKE executes it.

  diff.exe : diff.obj
	@bcc diff.obj


Using -num and -
- - - - - - - - -
The "-num" and "-" modifiers control MAKE processing under error
conditions. You can choose to continue with the MAKE process if an
error occurs or only if the errors exceed a given number.

In the following example, MAKE continues processing if BCC isn't run
successfully:

  target.exe : target.obj
  target.obj : target.cpp
    bcc -c target.cpp


Using &
- - - -
The & modifier issues a command once for each dependent file. It is
especially useful for commands that don't take a list of files as
parameters. For example,

  copyall : file1.cpp file2.cpp
	&copy $** c:\temp

results in COPY being invoked twice as follows:

  copy file1.cpp c:\temp
  copy file2.cpp c:\temp

Without the & modifier, COPY would be called only once.

Command operators
- - - - - - - - -
You can use any operating system command in a MAKE commands section.
MAKE uses the normal operators (such as +, -, and so on), but it also
has other operators you can use.

Operator	Description
--------	-----------
<		Take the input for use by "command" from
		"file" rather than from standard input.

>		Send the output from "command" to "file".

>>		Append the output from "command" to "file".

<<		Create a temporary, inline file and use
		its contents as standard input to
		"command".

&&		Create a temporary file and insert its
		name in the makefile.

delimiter	Any character other than # and \ used
		with << and && as a starting and ending
		delimiter for a temporary file. Any
		characters on the same line and
		immediately following the starting
		delimiter are ignored. The closing
		"delimiter" must be written on a line by
		itself.


Debugging with temporary files
- - - - - - - - - - - - - - - -
Temporary files can help you debug a command set by placing the actual
commands MAKE executes into the temporary file. Temporary file names
start at MAKE0000.@@@, where the 0000 increments for each temporary
file you keep. You must place delimiters after && and at the end of
what you want sent to the temporary file (! is a good delimiter).

The following example shows && instructing MAKE to create a file of
the input to TLINK.

  prog.exe: A.obj B.obj
     TLINK /c &&!
     c0s.obj $**
     prog.exe
     prog.map
     maths.lib cs.lib
     !

The response file created by && contains these instructions:

     c0s.obj a.obj b.obj
     prog.exe
     prog.map
     maths.lib cs.lib


Using MAKE macros
=================
A MAKE macro is a string that is expanded (used) wherever the macro is
called in a makefile. Macros let you create template makefiles that
you can change to suit different projects. For example, to define a
macro called LIBNAME that represents the string "mylib.lib," type
"LIBNAME = mylib.lib". When MAKE encounters the macro "$(LIBNAME)", it
uses the string "mylib.lib".

If MAKE finds an undefined macro in a makefile, it looks for an
operating-system environment variable of that name (usually defined
with SET) and uses its definition as the expansion text. For example,
if you wrote "$(path)" in a makefile and never defined "path", MAKE would
use the text you defined for PATH in your AUTOEXEC.BAT. (See the
manuals for your operating system for information on defining
environment variables.)


Defining macros
---------------
The general syntax for defining a macro in a makefile is:

	MacroName = expansion_text

  o  "MacroName" is case-sensitive and is limited to 512 characters.

  o  "expansion_text" is limited to 4096 characters consisting of
     alpha-numeric characters, punc-tuation, and white space.

Each macro must be on a separate line in a makefile. Macros are
usually put at the top of the makefile. If MAKE finds more than one
definition for a "macroName", the new definition replaces the old one.

Macros can also be defined using the command-line option -D. More than
one macro can be defined by separating them with spaces. The following
examples show macros defined at the command line:

  make -Dsourcedir=c:\projecta
  make command="bcc -c"
  make command=bcc option=-c

The following differences in syntax exist between macros entered on
the command line and macros written in a makefile.