/* sndsSio.h - header file for Samsung SNDS100 serial driver */

/*
modification history
--------------------
01a,22aug99,ak created
*/

#ifndef __INCsndsSioh
#define __INCsndsSioh

#include "sioLib.h"


/* Register offsets from Base Address*/

#define SNDS_ULCON		0x0000		/*UART Line Control Registers*/
#define SNDS_UCON		0x0004		/*UART Control Register */
#define SNDS_USTAT		0x0008		/*UART Status Register */
#define SNDS_UTXBUF		0x000c		/*UART Transmit Buffer Register*/
#define SNDS_URXBUF		0x0010		/*UART Receive Buffer Register*/
#define SNDS_UBRDIV		0x0014		/*UART Baud Rate Divisor Register*/
#define SNDS_BRDCNT		0x0018		/*UART Baud Rate Count Register */
#define SNDS_BRDCLK		0x001c		/*UART Baud Rate Clock Monitor*/



/* Bit definitions within ULCON0/1 Line Control Register*/

#define PARITY_NONE 	0x00			/* Set No Parity*/
#define PARITY_ODD 	0x20			/* Set Odd Parity*/
#define PARITY_EVEN	0x28			/* Set Even Parity*/
#define ONE_STOP	0x00			/* One Stop Bit*/
#define WORD_LEN	0x03			/* Set Word Length 8*/
#define INT_CLK		0x00			/* Internal Clock Mode */
#define	EXT_CLK		0x40			/* External Clock Mode */


/* Bit definitions within UCON0/1 Control Register*/

#define UCON_RX		0x01			/* Receive Mode -Interrupt*/
#define UCON_STAT_EN	0x04			/* Status Interrrupt -Enable*/
#define UCON_TX		0x08			/* Transmit Mode-Interrupt*/
#define UCON_TX_DIS	0x01			/* Transmit Interrupt -Disable*/
#define UCON_DSR	0x20			/* Data Set Ready -Enable*/
#define UCON_BREAK	0x40			/* Set Break*/
#define UCON_RX_TX_RESET 0xe4		/* Rx and Tx Reset */

/* Bit definitions within USTAT0/1 Status Register*/

#define USTAT_DTR_LOW	0x10			/* DTR Enable */
#define USTAT_DTR_HIGH	0x00			/* DTR Disable*/
#define USTAT_TX_READY	0x40	 		/* Transmitter Ready for another char */
#define USTAT_RX_AVAIL	0x20	 		/* Character has arrived*/ 
#define USTAT_OVER_ERR  0x01			/* Over Run Error*/
#define USTAT_PAR_ERR   0x02			/* Parity Error*/
#define USTAT_FRAME_ERR 0x04			/* Frame Error*/ 
#define USTAT_RX_READY  0x20			/* Receive Data Buffer*/



/* UART Baud Rate Divisor Time Constant Value */

#define SNDS_CNT0_1200		(1536<<4)		/* Baud_Rate 1200*/
#define SNDS_CNT0_2400		(768<<4)		/* Baud_Rate 2400*/
#define SNDS_CNT0_4800		(384<<4)		/* Baud_Rate 4800*/
#define SNDS_CNT0_9600		(192<<4)		/* Baud_Rate 9600*/
#define SNDS_CNT0_19200		(96<<4)		/* Baud_Rate 19200*/
/*#define SNDS_CNT0_38400		(48<<4)	*/	/* Baud_Rate 38400*/
#define SNDS_CNT0_38400		(40<<4)		/* by hugh*/
#define SNDS_CNT0_57600		(32<<4)		/* Baud_Rate 57600*/
#define SNDS_CNT0_115200	(16<<4)		/* Baud_Rate 115200*/
#define SNDS_CNT0_230400	(8<<4)		/* Baud_Rate 230400*/
#define SNDS_CNT0_460800	(4<<4)		/* Baud_Rate 460800*/

#define SNDS_CNT1_VAL	0x00			/* Baud Rate Divisor Value*/


/* device and channel structures */

typedef struct
    {
    /* must be first */

    SIO_CHAN		sio;		/* standard SIO_CHAN element */

    /* callbacks */

    STATUS	        (*getTxChar) ();
    STATUS	        (*putRcvChar) ();
    void *	        getTxArg;
    void *	        putRcvArg;

    /* register addresses */

    UINT32 *	regs;		/*UART Registers*/
    UINT8		level;		/* Interrupt Level for this device*/
  

    /* misc */
    UINT32	    regDelta;	/* register address spacing */
    uint_t		options;	/* Hardware options */
    int         mode;          	/* current mode (interrupt or poll) */
    int         baudRate;       /* input clock frequency */

    } SNDS_CHAN;

/* function prototypes */

#if defined(__STDC__)

extern void 	sndsDevInit	(SNDS_CHAN *pChan); 
extern void 	sndsDevInit2	(SNDS_CHAN *pChan); 
extern void	sndsIntRcv	(SNDS_CHAN *pChan);
extern void	sndsIntTx	(SNDS_CHAN *pChan);

#else   /* __STDC__ */

extern void 	sndsDevInit	();
extern void 	sndsDevInit2	();
extern void	sndsIntRcv	();
extern void	sndsIntTx	();


#endif  /* __STDC__ */

#endif  /* __INCsndsSioh */