/////////////////////////////////////////////////////////////////////////////////////////////
//
// Altera upCore Bus Transaction Simulator Slave Memory Configuration File
//
// slavememory.cfg.dat
//
// This file is interpreted by apex20ke_atoms.v to initialise the memory space available
// through the PLD slave port.
// The address space is divided into 6 banks each of up to 65536 32-bit words.
// Banks should not overlap.
// Memory is little-endian.
//
// The initial contents of each bank are defined in Verilog compatible hex files
// 			slavememory.<bank number>.dat
//
//////////////////////////////////////////////////////////////////////////////////////////////
// FORMAT
// 
// ******** - Bank Start byte address
//         ******** - Bank End byte address 
//                 ++ - number of wait states incurred prior to first access 
//                   ** - number of wait states on subsequent accesses
// HHHHHHHHHHHHHHHHHHHH
// 
// Bank start addresses should be word aligned.
//
// |      ||      |++**
// 00000000000000FF0000			// Bank zero contains 255 bytes between 00 and FF 
// |      ||      |++**			// initialisation file: slavememory.0.dat
// |      ||      |||			// 0 wait states
//
// NB unused banks should be specified as all zeros
/////////////////////////////////////////////////////////////////////////////////////////////
//      |      |++**
//XXxxXXxxXXxxXX++**
9000000090000FFF0403 // Bank zero contains 255 bytes between 00 and FF
00000000000000000000// Bank 1
00000000000000000000
00000000000000000000
00000000000000000000
00000000000000000000 // Bank 5
/////////////////////////////////////////////////////////////////////////////////////////////