onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Processor Registers}
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r0
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r1
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r2
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r3
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r4
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r5
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r6
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r7
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r8
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r9
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/r12
add wave -noupdate -divider {AHB1 Bus}
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_clk
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_haddr
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_htrans
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hsize
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hburst
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hwrite
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hwdta
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hrdata
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hresp
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb1_hready
add wave -noupdate -divider {AHB2 Bus}
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_clk
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hmaster
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_haddr
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_htrans
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hsize
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hburst
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hwrite
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hwdata
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hrdata
add wave -noupdate -format Literal /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hresp
add wave -noupdate -format Logic /ahb_bus_tb/dut/embedded_stripe/lpm_instance/u_epxa10top/u_epxa10/thetiming/theinout/ahb2_hready
add wave -noupdate -divider {PLD Bus1}
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus1/HMASTER
add wave -noupdate -format Literal /ahb_bus_tb/dut/pld_bus1_decoder/HSEL
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HTRANS
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HADDR
add wave -noupdate -format Logic /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HWRITE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus1/HBURST
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Write_data_bus_mux_pld_bus1/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus1/HREADY
add wave -noupdate -divider {PLD Bus2}
add wave -noupdate -format Literal /ahb_bus_tb/dut/arbiter_pld_bus2/HMASTER
add wave -noupdate -format Literal /ahb_bus_tb/dut/pld_bus2_decoder/HSEL
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HTRANS
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HADDR
add wave -noupdate -format Logic /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HWRITE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Address_Control_mux_pld_bus2/HBURST
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Write_data_bus_mux_pld_bus2/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HRESP
add wave -noupdate -format Logic -radix binary /ahb_bus_tb/dut/Read_data_bus_and_Slave_Response_pld_bus2/HREADY
add wave -noupdate -divider -height 30 {Perpherials on PLD Bus 1}
add wave -noupdate -divider {Master 3 Single Write Transaction(On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/HCLK
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/start_trans
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/HBUSREQ
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/HGRANT
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master3_single_write/HADDR
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master3_single_write/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master3_single_write/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master3_single_write/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/HWRITE
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master3_single_write/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master3_single_write/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master3_single_write/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master3_single_write/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master3_single_write/machine_state
add wave -noupdate -divider {Master 4 Burst Write Transaction (On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/HCLK
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/start_trans
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/HBUSREQ
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/HGRANT
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master4_burst_write/HADDR
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master4_burst_write/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master4_burst_write/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master4_burst_write/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/HWRITE
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master4_burst_write/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master4_burst_write/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master4_burst_write/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master4_burst_write/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master4_burst_write/machine_state
add wave -noupdate -divider {Master 5 Burst Read(On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/HCLK
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/start_trans
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/HBUSREQ
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/HGRANT
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master5_burst_read/HADDR
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master5_burst_read/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master5_burst_read/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master5_burst_read/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/HWRITE
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master5_burst_read/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/Master5_burst_read/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master5_burst_read/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/Master5_burst_read/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/Master5_burst_read/machine_state
add wave -noupdate -divider {Slave 1 Single Transaction (On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/single_transaction_slave1/HCLOCK
add wave -noupdate -format Logic /ahb_bus_tb/dut/single_transaction_slave1/HSEL
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/single_transaction_slave1/HADDRESS
add wave -noupdate -format Literal /ahb_bus_tb/dut/single_transaction_slave1/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/single_transaction_slave1/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/single_transaction_slave1/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/single_transaction_slave1/HWRITE
add wave -noupdate -format Logic /ahb_bus_tb/dut/single_transaction_slave1/HREADY_in
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/single_transaction_slave1/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/single_transaction_slave1/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/single_transaction_slave1/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/single_transaction_slave1/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/single_transaction_slave1/slave_state
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/slave1_regfile/memory
add wave -noupdate -divider {Slave 2 Burst Transcation Slave (On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/burst_slave2/HCLOCK
add wave -noupdate -format Logic /ahb_bus_tb/dut/burst_slave2/HSEL
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/burst_slave2/HADDRESS
add wave -noupdate -format Literal /ahb_bus_tb/dut/burst_slave2/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/burst_slave2/HSIZE
add wave -noupdate -format Literal /ahb_bus_tb/dut/burst_slave2/HBURST
add wave -noupdate -format Logic /ahb_bus_tb/dut/burst_slave2/HWRITE
add wave -noupdate -format Logic /ahb_bus_tb/dut/burst_slave2/HREADY_in
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/burst_slave2/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/burst_slave2/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/burst_slave2/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/burst_slave2/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/burst_slave2/slave_state
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/slave2_regfile/memory
add wave -noupdate -divider {Slave 3 Narrow Slave (On PLD Bus 1)}
add wave -noupdate -format Logic /ahb_bus_tb/dut/narrow_slave3/HCLOCK
add wave -noupdate -format Logic /ahb_bus_tb/dut/narrow_slave3/HSEL
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/narrow_slave3/HADDRESS
add wave -noupdate -format Literal /ahb_bus_tb/dut/narrow_slave3/HTRANS
add wave -noupdate -format Literal /ahb_bus_tb/dut/narrow_slave3/HBURST
add wave -noupdate -format Literal /ahb_bus_tb/dut/narrow_slave3/HSIZE
add wave -noupdate -format Logic /ahb_bus_tb/dut/narrow_slave3/HWRITE
add wave -noupdate -format Logic /ahb_bus_tb/dut/narrow_slave3/HREADY_in
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/narrow_slave3/HWDATA
add wave -noupdate -format Literal -radix hexadecimal /ahb_bus_tb/dut/narrow_slave3/HRDATA
add wave -noupdate -format Literal /ahb_bus_tb/dut/narrow_slave3/HRESP
add wave -noupdate -format Logic /ahb_bus_tb/dut/narrow_slave3/HREADY
add wave -noupdate -format Literal /ahb_bus_tb/dut/narrow_slave3/slave_state