/*----------------------------------------------------------------------------------------
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   Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
   support information,  device programming or simulation file,  and any other
   associated  documentation or information  provided by  Altera  or a partner
   under  Altera's   Megafunction   Partnership   Program  may  be  used  only
   to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
   other  use  of such  megafunction  design,  netlist,  support  information,
   device programming or simulation file,  or any other  related documentation
   or information  is prohibited  for  any  other purpose,  including, but not
   limited to  modification,  reverse engineering,  de-compiling, or use  with
   any other  silicon devices,  unless such use is  explicitly  licensed under
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   intellectual property,  including patents,  copyrights,  trademarks,  trade
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----------------------------------------------------------------------------------------*/

	#include "../embedded_stripe.h"
	
	
	
	// Memory map for PLD Slaves 
 #define SLAVE4_BASE       EXC_PLD_BLOCK0_BASE + 0x10004
 #define SLAVE5_BASE       EXC_PLD_BLOCK0_BASE + 0x20000
 #define SLAVE6_BASE       EXC_PLD_BLOCK0_BASE + 0x40004
 #define SLAVE7_BASE       EXC_PLD_BLOCK0_BASE + 0x80004
 #define SLAVE8_BASE       EXC_PLD_BLOCK0_BASE + 0x100004
 #define SLAVE9_BASE       EXC_PLD_BLOCK0_BASE + 0x200008
 #define SRAM1_BASE	   EXC_SPSRAM_BLOCK1_BASE
 #define OPERAND1_REGISTER    SLAVE5_BASE + 0x04
 #define OPERAND2_REGISTER    SLAVE5_BASE + 0x08
 #define OPERATION_REGISTER   SLAVE5_BASE + 0x0C
 #define RESULT_LOW_REGISTER   SLAVE5_BASE + 0x10
 #define RESULT_HIGH_REGISTER SLAVE5_BASE + 0x14


	.globl Entry
	

Entry:
	b   Start
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected
	b   Unexpected

// Unexpected exception handler
Unexpected:
	b   Unexpected

// Start of main program

Start:
//Load data to be transferred
   
    mov r0, #97		        //Load Data in r0 to be transferred
    mov r1, #1		        //Load Data in r1 to be transferred
    mov r2, #2		        //Load Data in r2 to be transferred
    mov r3, #3		        //Load Data in r3 to be transferred
    mov r4, #4		        //Load Data in r4 to be transferred
    mov r5, #5		        //Load Data in r5 to be transferred
    mov r6, #6		        //Load Data in r6 to be transferred
    mov r7, #7		        //Load Data in r7 to be transferred
    mov r8, #8		        //Load Data in r8 to be transferred
    

//Single Write and Read to Slave 4 Single Transaction Slave
    
	ldr r12, =SLAVE4_BASE	//Load the base address for Slave 4 in r12
	str r0, [r12]			//Store data in base address of Slave 4
	ldr r9, [r12]			//Read data back from Slave 4

//Drive the ALU with the processor (slave 5 alu slave)
    
	ldr r12, =OPERAND1_REGISTER	 //Load the address for operand 1 in r12
	str r3, [r12]			     //Store the contents of r3 as operand 1
	
	ldr r12, =OPERAND2_REGISTER  //Load the address for operand 2 in r12
	str r4, [r12]			     //Store the contents of r4 as operand 2
	
	ldr r12, =OPERATION_REGISTER  //Load the address for the operation register in r12
	str r7, [r12]			      //Store the contents of r7 as operation(7 = MULT)
	
	ldr r12, =RESULT_LOW_REGISTER  //Load the address for the lower nibble of the result register in r12
	ldr r9, [r12]			       //Read back the result into register r9
	
//Burst Write and Read to Slave 6 Burst Transaction Slave

    ldr r12, =SLAVE6_BASE	//Load the base address for Slave 6 in r12
	stmia r12!, {r1-r8}	    //Write to Slave 6 a burst of 8 words
	//Read the data back backwards
	sub r12, r12, #4        //Decrement the address by a word
	ldr r1, [r12]	        //Load the last value bursted 
	sub r12, r12, #4        
	ldr r2, [r12]
	sub r12, r12, #4
	ldr r3, [r12]
	sub r12, r12, #4
	ldr r4, [r12]
	sub r12, r12, #4
	ldr r5, [r12]
	sub r12, r12, #4
	ldr r6, [r12]
	sub r12, r12, #4
	ldr r7, [r12]
	sub r12, r12, #4
	ldr r8, [r12]
	
//Single Write and Read to Slave 7 Single Transaction Slave
    
	ldr r12, =SLAVE7_BASE	//Load the base address for Slave 7 in r12
	str r0, [r12]			//Store data in base address of Slave 7
	ldr r9, [r12]			//Read data back from Slave 7
	
//Burst Write and Read to Slave 8 Burst Transaction Slave

    ldr r12, =SLAVE8_BASE	//Load the base address for Slave 8 in r12
	stmia r12!, {r1-r8}	    //Write to Slave 8 a burst of 8 words
	//Read the data back backwards
	sub r12, r12, #4        //Decrement the address by a word
	ldr r1, [r12]	        //Load the last value bursted 
	sub r12, r12, #4        
	ldr r2, [r12]
	sub r12, r12, #4
	ldr r3, [r12]
	sub r12, r12, #4
	ldr r4, [r12]
	sub r12, r12, #4
	ldr r5, [r12]
	sub r12, r12, #4
	ldr r6, [r12]
	sub r12, r12, #4
	ldr r7, [r12]
	sub r12, r12, #4
	ldr r8, [r12]
	
//Burst Write and Read to Slave 9 Wide Transaction Slave
    ldr r12, =SLAVE9_BASE	//Load the base address for Slave 9 in r12
	stmia r12!, {r1-r8}	    //Write to Slave 9 a burst of 8 words
	stmia r12!, {r1-r8}	    //Write to Slave 9 a burst of 8 words
	ldr r12, =SLAVE9_BASE	//Load the base address for Slave 9 in r12
	ldmia r12!, {r1-r8}
	ldmia r12!, {r1-r8}
	
//Burst Read from SRAM, Master 4 has loaded it with some data and the processor is now going to read it back
	
    ldr r12, =SRAM1_BASE	//Load the base address for SRAM1 base in r12
	ldmia r12!, {r1-r8}	    //First 8 words in SRAM
	ldmia r12!, {r1-r8}	    //Second 8 words in SRAM
	

	nop	// The first few unused memory locations are padded to prevent unknown
	nop	//rom contents causing Xs in simulation waveform (not actually required)
	nop
	nop