?? top.rpt
字號(hào):
cpldfit: version H.38 Xilinx Inc.
Fitter Report
Design Name: top Date: 10-19-2006, 4:37PM
Device Used: XC95144XL-5-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
34 /144 ( 24%) 95 /720 ( 13%) 97 /432 ( 22%) 16 /144 ( 11%) 13 /81 ( 16%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 5/18 17/54 12/90 1/11
FB2 5/18 15/54 10/90 1/10
FB3 0/18 0/54 0/90 0/10
FB4 15/18 16/54 41/90 2/10
FB5 1/18 16/54 8/90 1/10
FB6 1/18 9/54 4/90 1/10
FB7 6/18 15/54 16/90 2/10
FB8 1/18 9/54 4/90 1/10
----- ----- ----- -----
34/144 97/432 95/720 9/81
* - Resource is exhausted
** Global Control Resources **
Signal 'INT0' mapped onto global clock net GCK1.
Signal 'INT1' mapped onto global clock net GCK2.
Signal 'WR' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'RST' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 12 12 | I/O : 21 73
Output : 1 1 | GCK/IO : 3 3
Bidirectional : 8 8 | GTS/IO : 0 4
GCK : 3 3 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 25 25
** Power Data **
There are 34 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 9 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DATA<7> 4 9 FB1_2 11 I/O I/O STD FAST
DATA<6> 4 9 FB2_11 6 I/O I/O STD FAST
DATA<4> 4 9 FB4_2 87 I/O I/O STD FAST
DATA<5> 4 9 FB4_11 93 I/O I/O STD FAST
TINT 8 16 FB5_5 36 I/O O STD FAST
DATA<0> 4 9 FB6_2 74 I/O I/O STD FAST
DATA<2> 4 9 FB7_2 50 I/O I/O STD FAST
DATA<3> 4 9 FB7_11 56 I/O I/O STD FAST
DATA<1> 4 9 FB8_2 63 I/O I/O STD FAST
** 25 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
INTER<5> 2 2 FB1_15 STD RESET
INTER<4> 2 2 FB1_16 STD RESET
INTER<3> 2 2 FB1_17 STD RESET
INTER<2> 2 2 FB1_18 STD RESET
INTER<1> 1 1 FB2_15 STD RESET
INTER<0> 1 1 FB2_16 STD RESET
INTER<7> 2 2 FB2_17 STD RESET
INTER<6> 2 2 FB2_18 STD RESET
$OpTx$$OpTx$FX_DC$19_INV$90 1 2 FB4_5 STD
ENA<3> 2 6 FB4_6 STD RESET
ENA<2> 2 6 FB4_7 STD RESET
ENA<1> 2 6 FB4_8 STD RESET
ENA<0> 2 6 FB4_9 STD RESET
INTER<7>/INTER<7>_RSTF 3 7 FB4_10 STD
INTER<6>/INTER<6>_RSTF 3 7 FB4_12 STD
INTER<5>/INTER<5>_RSTF 3 7 FB4_13 STD
INTER<4>/INTER<4>_RSTF 3 7 FB4_14 STD
INTER<3>/INTER<3>_RSTF 3 7 FB4_15 STD
INTER<2>/INTER<2>_RSTF 3 7 FB4_16 STD
INTER<1>/INTER<1>_RSTF 3 7 FB4_17 STD
INTER<0>/INTER<0>_RSTF 3 7 FB4_18 STD
ENA<7> 2 6 FB7_15 STD RESET
ENA<6> 2 6 FB7_16 STD RESET
ENA<5> 2 6 FB7_17 STD RESET
ENA<4> 2 6 FB7_18 STD RESET
** 16 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
ADDR<2> FB1_11 17 I/O I
INT0 FB1_17 22~ GCK/I/O GCK
RST FB2_2 99~ GSR/I/O GSR
ADDR<3> FB2_12 7 I/O I
INT6 FB2_14 8 I/O I
INT5 FB2_15 9 I/O I
INT1 FB3_2 23~ GCK/I/O GCK
WR FB3_8 27~ GCK/I/O GCK/I
INT3 FB4_5 89 I/O I
ADDR<7> FB4_8 91 I/O I
INT4 FB4_9 92 I/O I
ADDR<1> FB4_17 97 I/O I
INT7 FB5_9 40 I/O I
RD FB7_17 61 I/O I
INT2 FB8_8 66 I/O I
ADDR<0> FB8_14 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 17/37
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
DATA<7> 4 0 0 1 FB1_2 11 I/O I/O
(unused) 0 0 0 5 FB1_3 12 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 13 I/O
(unused) 0 0 0 5 FB1_6 14 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 15 I/O
(unused) 0 0 0 5 FB1_9 16 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 17 I/O I
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 19 I/O
INTER<5> 2 0 0 3 FB1_15 20 I/O (b)
INTER<4> 2 0 0 3 FB1_16 (b) (b)
INTER<3> 2 0 0 3 FB1_17 22 GCK/I/O GCK
INTER<2> 2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 7: ENA<7> 13: INTER<3>/INTER<3>_RSTF
2: ADDR<0> 8: INT2 14: INTER<4>/INTER<4>_RSTF
3: ADDR<1> 9: INT3 15: INTER<5>/INTER<5>_RSTF
4: ADDR<2> 10: INT4 16: INTER<7>
5: ADDR<3> 11: INT5 17: RD
6: ADDR<7> 12: INTER<2>/INTER<2>_RSTF
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<7> XXXXXXX........XX....................... 9
INTER<5> ..........X...X......................... 2
INTER<4> .........X...X.......................... 2
INTER<3> ........X...X........................... 2
INTER<2> .......X...X............................ 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 15/39
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O GSR
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 3 GTS/I/O
(unused) 0 0 0 5 FB2_9 4 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
DATA<6> 4 0 0 1 FB2_11 6 I/O I/O
(unused) 0 0 0 5 FB2_12 7 I/O I
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 8 I/O I
INTER<1> 1 0 0 4 FB2_15 9 I/O I
INTER<0> 1 0 0 4 FB2_16 (b) (b)
INTER<7> 2 0 0 3 FB2_17 10 I/O (b)
INTER<6> 2 0 0 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 6: ADDR<7> 11: INTER<1>/INTER<1>_RSTF
2: ADDR<0> 7: ENA<6> 12: INTER<6>
3: ADDR<1> 8: INT6 13: INTER<6>/INTER<6>_RSTF
4: ADDR<2> 9: INT7 14: INTER<7>/INTER<7>_RSTF
5: ADDR<3> 10: INTER<0>/INTER<0>_RSTF 15: RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<6> XXXXXXX....X..X......................... 9
INTER<1> ..........X............................. 1
INTER<0> .........X.............................. 1
INTER<7> ........X....X.......................... 2
INTER<6> .......X....X........................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 23 GCK/I/O GCK
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 24 I/O
(unused) 0 0 0 5 FB3_6 25 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 27 GCK/I/O GCK/I
(unused) 0 0 0 5 FB3_9 28 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 29 I/O
(unused) 0 0 0 5 FB3_12 30 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 32 I/O
(unused) 0 0 0 5 FB3_15 33 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 34 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
DATA<4> 4 0 0 1 FB4_2 87 I/O I/O
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 0 5 FB4_4 (b)
$OpTx$$OpTx$FX_DC$19_INV$90
1 0 0 4 FB4_5 89 I/O I
ENA<3> 2 0 0 3 FB4_6 90 I/O (b)
ENA<2> 2 0 0 3 FB4_7 (b) (b)
ENA<1> 2 0 0 3 FB4_8 91 I/O I
ENA<0> 2 0 0 3 FB4_9 92 I/O I
INTER<7>/INTER<7>_RSTF
3 0 0 2 FB4_10 (b) (b)
DATA<5> 4 0 0 1 FB4_11 93 I/O I/O
INTER<6>/INTER<6>_RSTF
3 0 0 2 FB4_12 94 I/O (b)
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