?? top.rpt
字號(hào):
INTER<5>/INTER<5>_RSTF
3 0 0 2 FB4_13 (b) (b)
INTER<4>/INTER<4>_RSTF
3 0 0 2 FB4_14 95 I/O (b)
INTER<3>/INTER<3>_RSTF
3 0 0 2 FB4_15 96 I/O (b)
INTER<2>/INTER<2>_RSTF
3 0 0 2 FB4_16 (b) (b)
INTER<1>/INTER<1>_RSTF
3 0 0 2 FB4_17 97 I/O I
INTER<0>/INTER<0>_RSTF
3 0 0 2 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 7: DATA<0>.PIN 12: ENA<5>
2: ADDR<0> 8: DATA<1>.PIN 13: INTER<4>
3: ADDR<1> 9: DATA<2>.PIN 14: INTER<5>
4: ADDR<2> 10: DATA<3>.PIN 15: RD
5: ADDR<3> 11: ENA<4> 16: WR
6: ADDR<7>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<4> XXXXXX....X.X.X......................... 9
$OpTx$$OpTx$FX_DC$19_INV$90
.XX..................................... 2
ENA<3> .XXXXX...X.............................. 6
ENA<2> .XXXXX..X............................... 6
ENA<1> .XXXXX.X................................ 6
ENA<0> .XXXXXX................................. 6
INTER<7>/INTER<7>_RSTF
.XXXXXX........X........................ 7
DATA<5> XXXXXX.....X.XX......................... 9
INTER<6>/INTER<6>_RSTF
.XXXXXX........X........................ 7
INTER<5>/INTER<5>_RSTF
.XXXXXX........X........................ 7
INTER<4>/INTER<4>_RSTF
.XXXXXX........X........................ 7
INTER<3>/INTER<3>_RSTF
.XXXXXX........X........................ 7
INTER<2>/INTER<2>_RSTF
.XXXXXX........X........................ 7
INTER<1>/INTER<1>_RSTF
.XXXXXX........X........................ 7
INTER<0>/INTER<0>_RSTF
.XXXXXX........X........................ 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 35 I/O
(unused) 0 0 0 5 FB5_3 (b)
(unused) 0 0 \/2 3 FB5_4 (b) (b)
TINT 8 3<- 0 0 FB5_5 36 I/O O
(unused) 0 0 /\1 4 FB5_6 37 I/O (b)
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 39 I/O
(unused) 0 0 0 5 FB5_9 40 I/O I
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 41 I/O
(unused) 0 0 0 5 FB5_12 42 I/O
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 43 I/O
(unused) 0 0 0 5 FB5_15 46 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 49 I/O
(unused) 0 0 0 5 FB5_18 (b)
Signals Used by Logic in Function Block
1: ENA<0> 7: ENA<6> 12: INTER<3>
2: ENA<1> 8: ENA<7> 13: INTER<4>
3: ENA<2> 9: INTER<0> 14: INTER<5>
4: ENA<3> 10: INTER<1> 15: INTER<6>
5: ENA<4> 11: INTER<2> 16: INTER<7>
6: ENA<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
TINT XXXXXXXXXXXXXXXX........................ 16
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
DATA<0> 4 0 0 1 FB6_2 74 I/O I/O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 76 I/O
(unused) 0 0 0 5 FB6_6 77 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 78 I/O
(unused) 0 0 0 5 FB6_9 79 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 80 I/O
(unused) 0 0 0 5 FB6_12 81 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 82 I/O
(unused) 0 0 0 5 FB6_15 85 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 86 I/O
(unused) 0 0 0 5 FB6_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 4: ADDR<2> 7: ENA<0>
2: ADDR<0> 5: ADDR<3> 8: INTER<0>
3: ADDR<1> 6: ADDR<7> 9: RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<0> XXXXXXXXX............................... 9
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 15/39
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
DATA<2> 4 0 0 1 FB7_2 50 I/O I/O
(unused) 0 0 0 5 FB7_3 (b)
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 52 I/O
(unused) 0 0 0 5 FB7_6 53 I/O
(unused) 0 0 0 5 FB7_7 (b)
(unused) 0 0 0 5 FB7_8 54 I/O
(unused) 0 0 0 5 FB7_9 55 I/O
(unused) 0 0 0 5 FB7_10 (b)
DATA<3> 4 0 0 1 FB7_11 56 I/O I/O
(unused) 0 0 0 5 FB7_12 58 I/O
(unused) 0 0 0 5 FB7_13 (b)
(unused) 0 0 0 5 FB7_14 59 I/O
ENA<7> 2 0 0 3 FB7_15 60 I/O (b)
ENA<6> 2 0 0 3 FB7_16 (b) (b)
ENA<5> 2 0 0 3 FB7_17 61 I/O I
ENA<4> 2 0 0 3 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 6: ADDR<7> 11: ENA<2>
2: ADDR<0> 7: DATA<4>.PIN 12: ENA<3>
3: ADDR<1> 8: DATA<5>.PIN 13: INTER<2>
4: ADDR<2> 9: DATA<6>.PIN 14: INTER<3>
5: ADDR<3> 10: DATA<7>.PIN 15: RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<2> XXXXXX....X.X.X......................... 9
DATA<3> XXXXXX.....X.XX......................... 9
ENA<7> .XXXXX...X.............................. 6
ENA<6> .XXXXX..X............................... 6
ENA<5> .XXXXX.X................................ 6
ENA<4> .XXXXXX................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
DATA<1> 4 0 0 1 FB8_2 63 I/O I/O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 64 I/O
(unused) 0 0 0 5 FB8_6 65 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 66 I/O I
(unused) 0 0 0 5 FB8_9 67 I/O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 68 I/O
(unused) 0 0 0 5 FB8_12 70 I/O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 71 I/O I
(unused) 0 0 0 5 FB8_15 72 I/O
(unused) 0 0 0 5 FB8_16 (b)
(unused) 0 0 0 5 FB8_17 73 I/O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$19_INV$90 4: ADDR<2> 7: ENA<1>
2: ADDR<0> 5: ADDR<3> 8: INTER<1>
3: ADDR<1> 6: ADDR<7> 9: RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<1> XXXXXXXXX............................... 9
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$19_INV$90 <= (ADDR(1) AND ADDR(0));
DATA_I(0) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(0))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(0))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(0))));
DATA(0) <= DATA_I(0) when DATA_OE(0) = '1' else 'Z';
DATA_OE(0) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(1) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(1))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(1))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(1))));
DATA(1) <= DATA_I(1) when DATA_OE(1) = '1' else 'Z';
DATA_OE(1) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(2) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(2))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(2))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(2))));
DATA(2) <= DATA_I(2) when DATA_OE(2) = '1' else 'Z';
DATA_OE(2) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(3) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(3))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(3))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(3))));
DATA(3) <= DATA_I(3) when DATA_OE(3) = '1' else 'Z';
DATA_OE(3) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(4) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(4))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(4))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(4))));
DATA(4) <= DATA_I(4) when DATA_OE(4) = '1' else 'Z';
DATA_OE(4) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(5) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(5))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(5))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(5))));
DATA(5) <= DATA_I(5) when DATA_OE(5) = '1' else 'Z';
DATA_OE(5) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
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