?? top.rpt
字號:
DATA_I(6) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(6))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(6))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(6))));
DATA(6) <= DATA_I(6) when DATA_OE(6) = '1' else 'Z';
DATA_OE(6) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
DATA_I(7) <= NOT (((ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(0) AND NOT ENA(7))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0) AND NOT INTER(7))
OR (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0) AND NOT INTER(7))));
DATA(7) <= DATA_I(7) when DATA_OE(7) = '1' else 'Z';
DATA_OE(7) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT RD AND
NOT $OpTx$$OpTx$FX_DC$19_INV$90);
FDCPE_ENA0: FDCPE port map (ENA(0),DATA(0).PIN,WR,RST,'0',ENA_CE(0));
ENA_CE(0) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA1: FDCPE port map (ENA(1),DATA(1).PIN,WR,RST,'0',ENA_CE(1));
ENA_CE(1) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA2: FDCPE port map (ENA(2),DATA(2).PIN,WR,RST,'0',ENA_CE(2));
ENA_CE(2) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA3: FDCPE port map (ENA(3),DATA(3).PIN,WR,RST,'0',ENA_CE(3));
ENA_CE(3) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA4: FDCPE port map (ENA(4),DATA(4).PIN,WR,RST,'0',ENA_CE(4));
ENA_CE(4) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA5: FDCPE port map (ENA(5),DATA(5).PIN,WR,RST,'0',ENA_CE(5));
ENA_CE(5) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA6: FDCPE port map (ENA(6),DATA(6).PIN,WR,RST,'0',ENA_CE(6));
ENA_CE(6) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
FDCPE_ENA7: FDCPE port map (ENA(7),DATA(7).PIN,WR,RST,'0',ENA_CE(7));
ENA_CE(7) <= (ADDR(7) AND NOT ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0));
INTER(0)/INTER(0)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0)));
FDCPE_INTER0: FDCPE port map (INTER(0),'1',INT0,INTER(0)/INTER(0)_RSTF,'0');
INTER(1)/INTER(1)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND NOT ADDR(2) AND NOT ADDR(1) AND
ADDR(0)));
FDCPE_INTER1: FDCPE port map (INTER(1),'1',INT1,INTER(1)/INTER(1)_RSTF,'0');
FDCPE_INTER2: FDCPE port map (INTER(2),'1',INT2,INTER(2)/INTER(2)_RSTF,'0');
INTER(2)/INTER(2)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
NOT ADDR(0)));
FDCPE_INTER3: FDCPE port map (INTER(3),'1',INT3,INTER(3)/INTER(3)_RSTF,'0');
INTER(3)/INTER(3)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND
ADDR(0)));
INTER(4)/INTER(4)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND
NOT ADDR(0)));
FDCPE_INTER4: FDCPE port map (INTER(4),'1',INT4,INTER(4)/INTER(4)_RSTF,'0');
FDCPE_INTER5: FDCPE port map (INTER(5),'1',INT5,INTER(5)/INTER(5)_RSTF,'0');
INTER(5)/INTER(5)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND
ADDR(0)));
FDCPE_INTER6: FDCPE port map (INTER(6),'1',INT6,INTER(6)/INTER(6)_RSTF,'0');
INTER(6)/INTER(6)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND ADDR(2) AND ADDR(1) AND
NOT ADDR(0)));
INTER(7)/INTER(7)_RSTF <= ((DATA(0).PIN)
OR (NOT WR)
OR (ADDR(7) AND ADDR(3) AND ADDR(2) AND ADDR(1) AND
ADDR(0)));
FDCPE_INTER7: FDCPE port map (INTER(7),'1',INT7,INTER(7)/INTER(7)_RSTF,'0');
TINT <= NOT (((EXP10_.EXP)
OR (EXP11_.EXP)
OR (ENA(0) AND INTER(0))
OR (ENA(1) AND INTER(1))
OR (ENA(2) AND INTER(2))
OR (ENA(3) AND INTER(3))
OR (ENA(5) AND INTER(5))));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-5-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-5-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 KPR 52 KPR
3 KPR 53 KPR
4 KPR 54 KPR
5 VCC 55 KPR
6 DATA<6> 56 DATA<3>
7 ADDR<3> 57 VCC
8 INT6 58 KPR
9 INT5 59 KPR
10 KPR 60 KPR
11 DATA<7> 61 RD
12 KPR 62 GND
13 KPR 63 DATA<1>
14 KPR 64 KPR
15 KPR 65 KPR
16 KPR 66 INT2
17 ADDR<2> 67 KPR
18 KPR 68 KPR
19 KPR 69 GND
20 KPR 70 KPR
21 GND 71 ADDR<0>
22 INT0 72 KPR
23 INT1 73 KPR
24 KPR 74 DATA<0>
25 KPR 75 GND
26 VCC 76 KPR
27 WR 77 KPR
28 KPR 78 KPR
29 KPR 79 KPR
30 KPR 80 KPR
31 GND 81 KPR
32 KPR 82 KPR
33 KPR 83 TDO
34 KPR 84 GND
35 KPR 85 KPR
36 TINT 86 KPR
37 KPR 87 DATA<4>
38 VCC 88 VCC
39 KPR 89 INT3
40 INT7 90 KPR
41 KPR 91 ADDR<7>
42 KPR 92 INT4
43 KPR 93 DATA<5>
44 GND 94 KPR
45 TDI 95 KPR
46 KPR 96 KPR
47 TMS 97 ADDR<1>
48 TCK 98 VCC
49 KPR 99 RST
50 DATA<2> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-5-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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