?? top.rpt
字號:
cpldfit: version H.38 Xilinx Inc.
Fitter Report
Design Name: top Date: 10-19-2006, 2:16PM
Device Used: XC95144XL-5-TQ100
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
28 /144 ( 19%) 70 /720 ( 10%) 67 /432 ( 15%) 17 /144 ( 12%) 29 /81 ( 36%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 3/18 9/54 9/90 3/11
FB2 3/18 7/54 6/90 3/10
FB3 4/18 7/54 8/90 4/10
FB4 4/18 10/54 14/90 3/10
FB5 3/18 10/54 10/90 3/10
FB6 3/18 9/54 7/90 3/10
FB7 4/18 8/54 8/90 4/10
FB8 4/18 7/54 8/90 4/10
----- ----- ----- -----
28/144 67/432 70/720 27/81
* - Resource is exhausted
** Global Control Resources **
Signal 'WR' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'RST' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 14 14 | I/O : 41 73
Output : 19 19 | GCK/IO : 1 3
Bidirectional : 8 8 | GTS/IO : 0 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 43 43
** Power Data **
There are 28 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 27 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DATA<3> 4 8 FB1_2 11 I/O I/O STD FAST
DATA<4> 4 8 FB1_6 14 I/O I/O STD FAST
DACS 1 5 FB1_11 17 I/O O STD FAST
GPIOC<1> 2 6 FB2_11 6 I/O O STD FAST RESET
GPIOC<6> 2 6 FB2_14 8 I/O O STD FAST RESET
GPIOD<1> 2 6 FB2_17 10 I/O O STD FAST RESET
GPIOC<2> 2 6 FB3_5 24 I/O O STD FAST RESET
GPIOC<3> 2 6 FB3_9 28 I/O O STD FAST RESET
GPIOD<2> 2 6 FB3_12 30 I/O O STD FAST RESET
GPIOD<3> 2 6 FB3_15 33 I/O O STD FAST RESET
DATA<2> 4 8 FB4_2 87 I/O I/O STD FAST
DATA<6> 4 8 FB4_8 91 I/O I/O STD FAST
DATA<7> 4 8 FB4_12 94 I/O I/O STD FAST
DATA<1> 4 8 FB5_2 35 I/O I/O STD FAST
DATA<5> 4 8 FB5_8 39 I/O I/O STD FAST
GPIOC<0> 2 6 FB5_12 42 I/O O STD FAST RESET
DATA<0> 4 8 FB6_2 74 I/O I/O STD FAST
GPIOC<7> 2 6 FB6_8 78 I/O O STD FAST RESET
ADCS 1 5 FB6_12 81 I/O O STD FAST
GPIOC<5> 2 6 FB7_2 50 I/O O STD FAST RESET
GPIOD<5> 2 6 FB7_8 54 I/O O STD FAST RESET
GPIOD<6> 2 6 FB7_12 58 I/O O STD FAST RESET
GPIOD<7> 2 6 FB7_17 61 I/O O STD FAST RESET
GPIOC<4> 2 6 FB8_2 63 I/O O STD FAST RESET
GPIOD<0> 2 6 FB8_8 66 I/O O STD FAST RESET
GPIOD<4> 2 6 FB8_12 70 I/O O STD FAST RESET
LED 2 6 FB8_17 73 I/O O STD FAST RESET
** 1 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
$OpTx$FX_DC$17 2 4 FB4_18 STD
** 16 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
KEY<5> FB1_3 12 I/O I
ADDR<3> FB1_5 13 I/O I
WR FB1_17 22~ GCK/I/O GCK
RST FB2_2 99~ GSR/I/O GSR
ADDR<1> FB2_12 7 I/O I
KEY<7> FB3_6 25 I/O I
KEY<0> FB4_6 90 I/O I
RD FB4_9 92 I/O I
KEY<6> FB5_14 43 I/O I
KEY<3> FB6_6 77 I/O I
ADDR<2> FB6_9 79 I/O I
KEY<2> FB6_11 80 I/O I
ADDR<15> FB6_17 86 I/O I
KEY<4> FB7_9 55 I/O I
KEY<1> FB7_14 59 I/O I
ADDR<0> FB8_14 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
DATA<3> 4 0 0 1 FB1_2 11 I/O I/O
(unused) 0 0 0 5 FB1_3 12 I/O I
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 13 I/O I
DATA<4> 4 0 0 1 FB1_6 14 I/O I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 15 I/O
(unused) 0 0 0 5 FB1_9 16 I/O
(unused) 0 0 0 5 FB1_10 (b)
DACS 1 0 0 4 FB1_11 17 I/O O
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 22 GCK/I/O GCK
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$17 4: ADDR<1> 7: KEY<3>
2: ADDR<0> 5: ADDR<2> 8: KEY<4>
3: ADDR<15> 6: ADDR<3> 9: RD
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
DATA<3> XXXXXXX.X............................... 8
DATA<4> XXXXXX.XX............................... 8
DACS .XXXXX.................................. 5
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O GSR
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 3 GTS/I/O
(unused) 0 0 0 5 FB2_9 4 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
GPIOC<1> 2 0 0 3 FB2_11 6 I/O O
(unused) 0 0 0 5 FB2_12 7 I/O I
(unused) 0 0 0 5 FB2_13 (b)
GPIOC<6> 2 0 0 3 FB2_14 8 I/O O
(unused) 0 0 0 5 FB2_15 9 I/O
(unused) 0 0 0 5 FB2_16 (b)
GPIOD<1> 2 0 0 3 FB2_17 10 I/O O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: ADDR<0> 4: ADDR<2> 6: DATA<1>.PIN
2: ADDR<15> 5: ADDR<3> 7: DATA<6>.PIN
3: ADDR<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
GPIOC<1> XXXXXX.................................. 6
GPIOC<6> XXXXX.X................................. 6
GPIOD<1> XXXXXX.................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 23 GCK/I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
GPIOC<2> 2 0 0 3 FB3_5 24 I/O O
(unused) 0 0 0 5 FB3_6 25 I/O I
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 27 GCK/I/O
GPIOC<3> 2 0 0 3 FB3_9 28 I/O O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 29 I/O
GPIOD<2> 2 0 0 3 FB3_12 30 I/O O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 32 I/O
GPIOD<3> 2 0 0 3 FB3_15 33 I/O O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 34 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: ADDR<0> 4: ADDR<2> 6: DATA<2>.PIN
2: ADDR<15> 5: ADDR<3> 7: DATA<3>.PIN
3: ADDR<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
GPIOC<2> XXXXXX.................................. 6
GPIOC<3> XXXXX.X................................. 6
GPIOD<2> XXXXXX.................................. 6
GPIOD<3> XXXXX.X................................. 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
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