?? top.rpt
字號:
DATA_I(4) <= NOT (((ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
NOT ADDR(0))
OR (ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND
ADDR(0))
OR (NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND ADDR(0) AND
NOT KEY(4))));
DATA(4) <= DATA_I(4) when DATA_OE(4) = '1' else 'Z';
DATA_OE(4) <= (ADDR(15) AND NOT RD AND $OpTx$FX_DC$17);
DATA_I(5) <= NOT (((ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
NOT ADDR(0))
OR (ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND
ADDR(0))
OR (NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND ADDR(0) AND
NOT KEY(5))));
DATA(5) <= DATA_I(5) when DATA_OE(5) = '1' else 'Z';
DATA_OE(5) <= (ADDR(15) AND NOT RD AND $OpTx$FX_DC$17);
DATA_I(6) <= NOT (((ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
NOT ADDR(0))
OR (ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND
ADDR(0))
OR (NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND ADDR(0) AND
NOT KEY(6))));
DATA(6) <= DATA_I(6) when DATA_OE(6) = '1' else 'Z';
DATA_OE(6) <= (ADDR(15) AND NOT RD AND $OpTx$FX_DC$17);
DATA_I(7) <= NOT (((ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
NOT ADDR(0))
OR (ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND
ADDR(0))
OR (NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND ADDR(0) AND
NOT KEY(7))));
DATA(7) <= DATA_I(7) when DATA_OE(7) = '1' else 'Z';
DATA_OE(7) <= (ADDR(15) AND NOT RD AND $OpTx$FX_DC$17);
FDCPE_GPIOC0: FDCPE port map (GPIOC(0),DATA(0).PIN,WR,RST,'0',GPIOC_CE(0));
GPIOC_CE(0) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC1: FDCPE port map (GPIOC(1),DATA(1).PIN,WR,RST,'0',GPIOC_CE(1));
GPIOC_CE(1) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC2: FDCPE port map (GPIOC(2),DATA(2).PIN,WR,RST,'0',GPIOC_CE(2));
GPIOC_CE(2) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC3: FDCPE port map (GPIOC(3),DATA(3).PIN,WR,RST,'0',GPIOC_CE(3));
GPIOC_CE(3) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC4: FDCPE port map (GPIOC(4),DATA(4).PIN,WR,RST,'0',GPIOC_CE(4));
GPIOC_CE(4) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC5: FDCPE port map (GPIOC(5),DATA(5).PIN,WR,RST,'0',GPIOC_CE(5));
GPIOC_CE(5) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC6: FDCPE port map (GPIOC(6),DATA(6).PIN,WR,RST,'0',GPIOC_CE(6));
GPIOC_CE(6) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOC7: FDCPE port map (GPIOC(7),DATA(7).PIN,WR,RST,'0',GPIOC_CE(7));
GPIOC_CE(7) <= (ADDR(3) AND ADDR(2) AND NOT ADDR(1) AND ADDR(15) AND
ADDR(0));
FDCPE_GPIOD0: FDCPE port map (GPIOD(0),DATA(0).PIN,WR,RST,'0',GPIOD_CE(0));
GPIOD_CE(0) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD1: FDCPE port map (GPIOD(1),DATA(1).PIN,WR,RST,'0',GPIOD_CE(1));
GPIOD_CE(1) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD2: FDCPE port map (GPIOD(2),DATA(2).PIN,WR,RST,'0',GPIOD_CE(2));
GPIOD_CE(2) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD3: FDCPE port map (GPIOD(3),DATA(3).PIN,WR,RST,'0',GPIOD_CE(3));
GPIOD_CE(3) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD4: FDCPE port map (GPIOD(4),DATA(4).PIN,WR,RST,'0',GPIOD_CE(4));
GPIOD_CE(4) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD5: FDCPE port map (GPIOD(5),DATA(5).PIN,WR,RST,'0',GPIOD_CE(5));
GPIOD_CE(5) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD6: FDCPE port map (GPIOD(6),DATA(6).PIN,WR,RST,'0',GPIOD_CE(6));
GPIOD_CE(6) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_GPIOD7: FDCPE port map (GPIOD(7),DATA(7).PIN,WR,RST,'0',GPIOD_CE(7));
GPIOD_CE(7) <= (ADDR(3) AND ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
FDCPE_LED: FDCPE port map (LED,DATA(0).PIN,WR,RST,'0',LED_CE);
LED_CE <= (NOT ADDR(3) AND NOT ADDR(2) AND ADDR(1) AND ADDR(15) AND
NOT ADDR(0));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-5-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC95144XL-5-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 KPR 51 VCC
2 KPR 52 KPR
3 KPR 53 KPR
4 KPR 54 GPIOD<5>
5 VCC 55 KEY<4>
6 GPIOC<1> 56 KPR
7 ADDR<1> 57 VCC
8 GPIOC<6> 58 GPIOD<6>
9 KPR 59 KEY<1>
10 GPIOD<1> 60 KPR
11 DATA<3> 61 GPIOD<7>
12 KEY<5> 62 GND
13 ADDR<3> 63 GPIOC<4>
14 DATA<4> 64 KPR
15 KPR 65 KPR
16 KPR 66 GPIOD<0>
17 DACS 67 KPR
18 KPR 68 KPR
19 KPR 69 GND
20 KPR 70 GPIOD<4>
21 GND 71 ADDR<0>
22 WR 72 KPR
23 KPR 73 LED
24 GPIOC<2> 74 DATA<0>
25 KEY<7> 75 GND
26 VCC 76 KPR
27 KPR 77 KEY<3>
28 GPIOC<3> 78 GPIOC<7>
29 KPR 79 ADDR<2>
30 GPIOD<2> 80 KEY<2>
31 GND 81 ADCS
32 KPR 82 KPR
33 GPIOD<3> 83 TDO
34 KPR 84 GND
35 DATA<1> 85 KPR
36 KPR 86 ADDR<15>
37 KPR 87 DATA<2>
38 VCC 88 VCC
39 DATA<5> 89 KPR
40 KPR 90 KEY<0>
41 KPR 91 DATA<6>
42 GPIOC<0> 92 RD
43 KEY<6> 93 KPR
44 GND 94 DATA<7>
45 TDI 95 KPR
46 KPR 96 KPR
47 TMS 97 KPR
48 TCK 98 VCC
49 KPR 99 RST
50 GPIOC<5> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-5-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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