?? dma54xx.h
字號:
FRAMECOUNT_SZ, value)
/******************************************************************/
/* DMA_INTMASK_ENABLE - enable DMA interrupt */
/* */
/******************************************************************/
#define DMA_INTMASK_ENABLE(chan) \
DMA_SUBREG_BITWRITE(chan, DMMCR_SUBADDR, DINM, DINM_SZ, DINM_ENABLE)
/******************************************************************/
/* DMA_INTMASK_DISABLE - disable DMA interrupt */
/* */
/******************************************************************/
#define DMA_INTMASK_DISABLE(chan) \
DMA_SUBREG_BITWRITE(chan, DMMCR_SUBADDR, DINM, DINM_SZ, DINM_DISABLE)
/******************************************************************/
/* DMA_DMS_SELECT - set Source Space Select */
/* */
/******************************************************************/
#define DMA_DMS_SELECT(chan, value) \
DMA_SUBREG_BITWRITE(chan, DMMCR_SUBADDR, DMS, DMS_SZ, value)
/******************************************************************/
/* DMA_DMD_SELECT - set Destination Space Select */
/* */
/******************************************************************/
#define DMA_DMD_SELECT(chan, value) \
DMA_SUBREG_BITWRITE(chan, DMMCR_SUBADDR, DMD, DMD_SZ, value)
/*-----------------------------------------------------------------------------*/
/* FUNCTION DEFINITIONS */
/*-----------------------------------------------------------------------------*/
/******************************************************************************/
/* dma_init - Initialize channel specific control registers. */
/* */
/* This function is responsible for setting the DMA control registers, */
/* source address, destination address and the corresponding pages */
/* transfer count for the specified DMA channel. */
/* */
/******************************************************************************/
__INLINE void dma_init( /*RET: OK or ERROR (invalid channel) */
unsigned int channel /*IN: DMA channel number */
,unsigned int dmsefc /*IN: Value to set sync & fr reg */
,unsigned int dmmcr /*IN: Value to set mode control reg */
,unsigned int dmctr /*IN: Value to set element count reg */
,unsigned int src_page /*IN: Value to set source page reg */
,unsigned int src_addr /*IN: Value to set source addr reg */
,unsigned int dst_page /*IN: Value to set dest page reg */
,unsigned int dst_addr /*IN: Value to set dest addr reg */
);
/******************************************************************************/
/* dma_global_init - Initialize global control registers. */
/* */
/* This function is responsible for setting the DMA global control */
/* registers */
/* Notice: DMDSTP and DMSRCP are used in DMA_GLOBAL_INIT and DMA_INIT */
/* necessity should be reconsidered */
/******************************************************************************/
__INLINE void dma_global_init( /*RET: VOID function */
unsigned int dmpre /*IN:Value for priority and enable reg*/
,unsigned int dmsrcp /*IN:Value for source page reg */
,unsigned int dmdstp /*IN:Value for dest page reg */
,unsigned int dmidx0 /*IN:Value for element index reg 0 */
,unsigned int dmidx1 /*IN:Value for element index reg 1 */
,unsigned int dmfri0 /*IN:Value for frame index reg 0 */
,unsigned int dmfri1 /*IN:Value for frame index reg 1 */
,unsigned int dmgsa /*IN:Value for global src addr reload */
,unsigned int dmgda /*IN:Value for global dst addr reload */
,unsigned int dmgcr /*IN:Value for global count reload reg*/
,unsigned int dmgfr /*IN:Value for global frame reload reg*/
);
/******************************************************************************/
/* dma_reset_all - Reset DMA channel. */
/* */
/* This function resets the specified DMA channel by initializing */
/* channel control registers to their default values */
/* */
/* */
/******************************************************************************/
__INLINE void dma_reset_all(void);
__INLINE void dma_reset(unsigned int channel);
#if _INLINE
static inline void dma_init(
unsigned int channel /*IN: DMA channel number */
,unsigned int dmsefc /*IN: Value to set sync & fr reg */
,unsigned int dmmcr /*IN: Value to set mode control reg */
,unsigned int dmctr /*IN: Value to set element count reg */
,unsigned int src_page /*IN: Value to set source page reg */
,unsigned int src_addr /*IN: Value to set source addr reg */
,unsigned int dst_page /*IN: Value to set dest page reg */
,unsigned int dst_addr /*IN: Value to set dest addr reg */
)
{
DMA_SUBREG_WRITE(channel, DMSRC_SUBADDR, src_addr);
REG_WRITE(DMSAI_ADDR, dst_addr);
REG_WRITE(DMSAI_ADDR, dmctr);
REG_WRITE(DMSAI_ADDR, dmsefc);
REG_WRITE(DMSAI_ADDR, dmmcr);
DMA_SUBREG_WRITE(channel, DMSRCP_SUBADDR, src_page);
REG_WRITE(DMSAI, dst_page);
}
static inline void dma_global_init(
unsigned int dmpre /*IN:Value for priority and enable reg*/
,unsigned int dmsrcp /*IN:Value for source page reg */
,unsigned int dmdstp /*IN:Value for dest page reg */
,unsigned int dmidx0 /*IN:Value for element index reg 0 */
,unsigned int dmidx1 /*IN:Value for element index reg 1 */
,unsigned int dmfri0 /*IN:Value for frame index reg 0 */
,unsigned int dmfri1 /*IN:Value for frame index reg 1 */
,unsigned int dmgsa /*IN:Value for global src addr reload */
,unsigned int dmgda /*IN:Value for global dst addr reload */
,unsigned int dmgcr /*IN:Value for global count reload reg*/
,unsigned int dmgfr) /*IN:Value for global frame reload reg*/
{
REG_WRITE(DMPRE_ADDR, dmpre);
DMA_SUBREG_WRITE(0, DMSRCP_SUBADDR, dmsrcp);
REG_WRITE(DMSAI_ADDR, dmdstp);
REG_WRITE(DMSAI_ADDR, dmidx0);
REG_WRITE(DMSAI_ADDR, dmidx1);
REG_WRITE(DMSAI_ADDR, dmfri0);
REG_WRITE(DMSAI_ADDR, dmfri1);
REG_WRITE(DMSAI_ADDR, dmgsa);
REG_WRITE(DMSAI_ADDR, dmgda);
REG_WRITE(DMSAI_ADDR, dmgcr);
REG_WRITE(DMSAI_ADDR, dmgfr);
}
static inline void dma_reset_all( void )
{
int channel;
REG_WRITE(DMPRE_ADDR, 0x00);
for (channel= 0;channel < 5; channel++)
{
DMA_SUBREG_WRITE(channel, DMSRC_SUBADDR, 0x00);
REG_WRITE(DMSAI_ADDR, 0x00); //src
REG_WRITE(DMSAI_ADDR, 0x00); //dst
REG_WRITE(DMSAI_ADDR, 0x00); //ctr
REG_WRITE(DMSAI_ADDR, 0x00); //sefc
REG_WRITE(DMSAI_ADDR, 0x00); //mcr
}
DMA_SUBREG_WRITE(channel, DMSRCP_SUBADDR, 0x00);
REG_WRITE(DMSAI_ADDR, 0x00); /*DMDSTP*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMIDX0*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMIDX1*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMFRI0*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMFRI1*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMGSA*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMGDA*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMGCR*/
REG_WRITE(DMSAI_ADDR, 0x00); /*DMGRF*/
}
static inline void dma_reset( unsigned int channel )
{
RESET_BIT(DMPRE_ADDR, channel); //disable channel
RESET_BIT(DMPRE_ADDR, channel+8); //set priority low
DMA_SUBREG_WRITE(channel, DMSRC_SUBADDR, 0x00);
REG_WRITE(DMSAI_ADDR, 0x00); //src
REG_WRITE(DMSAI_ADDR, 0x00); //dst
REG_WRITE(DMSAI_ADDR, 0x00); //ctr
REG_WRITE(DMSAI_ADDR, 0x00); //sefc
REG_WRITE(DMSAI_ADDR, 0x00); //mcr
}
#endif /* _INLINE */
#undef __INLINE
#endif /* _DMA_H_ */
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