?? hplpxa27xinterruptimplm.nc
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// $Id: HplPXA27xInterruptImplM.nc,v 1.1 2008/06/12 14:02:31 klueska Exp $
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/*
*
* Authors: Phil Buonadonna
*
* Edits: Josh Herbach
* Revised: 09/02/2005
*
* Edits: Kevin Klues
* Revised: 05/27/2008
*/
module HplPXA27xInterruptM
{
provides {
interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];
interface HplPXA27xInterruptCntl;
}
uses interface PlatformInterrupt;
}
implementation
{
uint32_t getICHP() {
uint32_t val;
asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));
return val;
}
/* Core PXA27X interrupt dispatch vectors */
/* DO NOT change the name of these functions */
void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {
uint32_t IRQPending;
IRQPending = getICHP(); // Determine which interrupt to service
IRQPending >>= 16; // Right justify to the IRQ portion
while (IRQPending & (1 << 15)) {
uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit
signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt
call PlatformInterrupt.postAmble();
IRQPending = getICHP(); // Determine which interrupt to service
IRQPending >>= 16; // Right justify to the IRQ portion
}
return;
}
void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {
call PlatformInterrupt.postAmble();
}
static uint8_t usedPriorities = 0;
/* Helper functions */
/* NOTE: Read-back of all register writes is necessary to ensure the data latches */
error_t allocate(uint8_t id, bool level, uint8_t priority)
{
uint32_t tmp;
error_t error = FAIL;
atomic{
uint8_t i;
if(usedPriorities == 0){//assumed that the table will have some entries
uint8_t PriorityTable[40], DuplicateTable[40];
for(i = 0; i < 40; i++){
DuplicateTable[i] = PriorityTable[i] = 0xFF;
}
for(i = 0; i < 40; i++)
if(TOSH_IRP_TABLE[i] != 0xff){
if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities
in the table, mark
for later fixing*/
DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];
else
PriorityTable[TOSH_IRP_TABLE[i]] = i;
}
//compress table
for(i = 0; i < 40; i++){
if(PriorityTable[i] != 0xff){
PriorityTable[usedPriorities] = PriorityTable[i];
if(i != usedPriorities)
PriorityTable[i] = 0xFF;
usedPriorities++;
}
}
for(i = 0; i < 40; i++)
if(DuplicateTable[i] != 0xFF){
uint8_t j, ExtraTable[40];
for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);
memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);
memcpy(PriorityTable + j + 1, ExtraTable + j + 1,
usedPriorities - j);
PriorityTable[j] = i;
usedPriorities++;
}
for(i = 0; i < usedPriorities; i++){
IPR(i) = (IPR_VALID | PriorityTable[i]);
tmp = IPR(i);
}
}
if (id < 34){
if(priority == 0xff){
priority = usedPriorities;
usedPriorities++;
IPR(priority) = (IPR_VALID | (id));
tmp = IPR(priority);
}
if (level) {
_ICLR(id) |= _PPID_Bit(id);
tmp = _ICLR(id);
}
error = SUCCESS;
}
}
return error;
}
void enable(uint8_t id)
{
uint32_t tmp;
atomic {
if (id < 34) {
_ICMR(id) |= _PPID_Bit(id);
tmp = _ICMR(id);
}
}
return;
}
void disable(uint8_t id)
{
uint32_t tmp;
atomic {
if (id < 34) {
_ICMR(id) &= ~(_PPID_Bit(id));
tmp = _ICMR(id);
}
}
return;
}
/* Interface implementation */
async command error_t PXA27xIrq.allocate[uint8_t id]()
{
return allocate(id, FALSE, TOSH_IRP_TABLE[id]);
}
async command void PXA27xIrq.enable[uint8_t id]()
{
enable(id);
return;
}
async command void PXA27xIrq.disable[uint8_t id]()
{
disable(id);
return;
}
async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {
if (flag) {
ICCR |= ICCR_DIM;
}
else {
ICCR = 0;
}
return;
}
async command bool HplPXA27xInterruptCntl.getICCR_DIM() {
bool result = FALSE;
if (ICCR & ICCR_DIM) {
result = TRUE;
}
return result;
}
default async event void PXA27xIrq.fired[uint8_t id]()
{
return;
}
}
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