/****************************************************************
KPIT Cummins Infosystems Ltd, Pune, India. 1-April-2006.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

*****************************************************************/
/****************************************************************/
/*      M16C/60 62P Include File                                */
/****************************************************************/

#ifndef __IOM16C62P_H__
#define __IOM16C62P_H__

/*------------------------------------------------------
    Processor mode register 0  //0x0004
------------------------------------------------------*/
union st_pm0 {               /* union PM0    	   					*/
  struct {             		 /* Bit  Access 		   			*/
	 unsigned char 	PM0_0:1; /* Processor mode bit 0 				*/
	 unsigned char 	PM0_1:1; /* Processor mode bit 1 				*/
	 unsigned char 	PM0_2:1; /* R/W mode select bit  				*/
	 unsigned char 	PM0_3:1; /* Software reset bit					*/
	 unsigned char 	PM0_4:1; /* Multiplexed bus space select bit 0	*/
	 unsigned char 	PM0_5:1; /* Multiplexed bus space select bit 1	*/
	 unsigned char 	PM0_6:1; /* Port P40 to P43 function select bit */
	 unsigned char 	PM0_7:1; /* BCLK output disable bit		      	*/
  } BIT;   		     		 /*        						    	*/
	unsigned  char BYTE;     /*  Byte Access 						*/
};                           /* 						            */

/*------------------------------------------------------
    Processor mode register 1  //0x0005
------------------------------------------------------*/
union st_pm1 {              /* union PM1    	   					 */
  struct {            		/* Bit  Access 		   				 */
	 unsigned char PM1_0:1; /* CS2 area switching bit                */
	 unsigned char PM1_1:1; /* Port P3_4 to P3_7 function select bit */
	 unsigned char PM1_2:1; /* Watch dog timer function select bit   */
	 unsigned char PM1_3:1; /* Intermal reserved area expansion bit  */
	 unsigned char PM1_4:1; /* Memory area expansion bit             */
	 unsigned char PM1_5:1; /* Memory area expansion bit             */
	 unsigned char PM1_6:1; /* Reserved bit  					 */
	 unsigned char PM1_7:1; /* PM17 - Wait bit				    	 */
  } BIT;   		    		/*        					 */
	 unsigned char BYTE;    /*  Byte Access 					 */
};                          /* 						            	 */

/*------------------------------------------------------
    System clock control register 0  //0x0006
------------------------------------------------------*/
union st_cm0 {               /* union CM0    	   					*/
  struct {             		 /* Bit  Access 		   			*/
	 unsigned char 	CM0_0:1; /* Clock output function select bit 	*/
	 unsigned char 	CM0_1:1; /* Clock output function select bit 	*/
	 unsigned char 	CM0_2:1; /* WAIT peripheral function clock stop bit */
	 unsigned char 	CM0_3:1; /* Xcin-Xcout drive capacity select bit*/
	 unsigned char 	CM0_4:1; /* Port Xc select bit 					*/
	 unsigned char 	CM0_5:1; /* Main clock stop bit					*/
	 unsigned char 	CM0_6:1; /* Main clock division select bit 0 	*/
	 unsigned char 	CM0_7:1; /* System clock select bit 			*/
  } BIT;   		     		 /*        					*/
	unsigned char BYTE;      /*  Byte Access 					*/
};                           /* system clock control register  0    */


/*------------------------------------------------------
    System clock control register 1 //0x0007
------------------------------------------------------*/
union st_cm1 {               /* union CM1    	   					*/
  struct {             		 /* Bit  Access 		   			*/
	 unsigned char 	CM1_0:1; /* All clock stop control bit 			*/
	 unsigned char 	CM1_1:1; /* Reserved bit always set to 0		*/
	 unsigned char 	 	 :1; /* Reserved bit always set to 0		*/
	 unsigned char 		 :1; /* Reserved bit always set to 0		*/
	 unsigned char 		 :1; /* Reserved bit always set to 0		*/
	 unsigned char 	CM1_5:1; /* Xin-Xouts drive capacity select bit */
	 unsigned char 	CM1_6:1; /* Main clock division select bit 1 	*/
	 unsigned char 	CM1_7:1; /* Main clock division select bit 1 	*/
  } BIT;   		     		 /*        				    */
	unsigned char BYTE;      /*  Byte Access 					*/
};                           /* system clock control register 1     */


/*------------------------------------------------------
    Chip select control register //0x0008
------------------------------------------------------*/
union st_csr {               /* union CSR    	   					*/
   struct {             	 /* Bit  Access 		   			*/
	 unsigned char	CS0 :1;  /* CS0~ output enable bit				*/
	 unsigned char	CS1 :1;  /* CS1~ output enable bit 				*/
	 unsigned char	CS2 :1;  /* CS2~ output enable bit 				*/
	 unsigned char	CS3 :1;  /* CS3~ output enable bit 				*/
	 unsigned char	CS0W:1;  /* CS0~ wait bit 					*/
	 unsigned char	CS1W:1;  /* CS1~ wait bit 					*/
	 unsigned char	CS2W:1;  /* CS2~ wait bit 					*/
	 unsigned char	CS3W:1;  /* CS3~ wait bit 					*/
   } BIT;   		         /*        						*/
	 unsigned char BYTE;     /* Byte Access 					*/
};                           /* Chip select control register		*/

/*------------------------------------------------------
    Address match interrupt enable register //0x0009
------------------------------------------------------*/
union st_aier {               /* union AIER    	   					*/
   struct {              	  /* Bit  Access 		   				*/
	 unsigned char 	AIER0:1;  /* Address match interrupt0 enable bit*/
	 unsigned char 	AIER1:1;  /* Address match interrupt1 enable bit*/
	 unsigned char 		 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
	 unsigned char 	 	 :1;  /* Nothing assigned 					*/
	 unsigned char 		 :1;  /* Nothing assigned  					*/
   } BIT;   		      	  /*       						    	*/
	 unsigned char BYTE;      /* Byte Access 						*/
};                            /* Address match interrupt enable register	*/


/*------------------------------------------------------
   Protect register //0x000A
-----------------------------------------------------*/
union st_prcr {               /* union PRCR    	   					*/
   struct {              	  /* Bit  Access 		   				*/
	 unsigned char 	PRC0:1;   /* Enables writing to system clock control registers 0 & 1 */
	 unsigned char 	PRC1:1;   /* Enables writing to processor mode registers 0 & 1 */
	 unsigned char 	PRC2:1;   /* Enables writing to port P9 direction register & SI/Oi control register(i=3,4)*/
	 unsigned char 	PRC3:1;   /* Enable writting to Power supply detection register 2 and Power supply down detection register */
	 unsigned char 		:1;   /* Nothing assigned  					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
	 unsigned char 	 	:1;   /* Nothing assigned 					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
   } BIT;   		      	  /*       						    	*/
	 unsigned char BYTE;      /* Byte Access 						*/
};                            /* Protect register					*/

/*------------------------------------------------------
	Data bank register //0x000B
------------------------------------------------------*/
union st_dbr {                /* union DBR   	   					*/
   struct {              	  /* Bit  Access 		   				*/
	 unsigned char 	    :1;   /* Nothing assigned  					*/
	 unsigned char 	    :1;   /* Nothing assigned  					*/
	 unsigned char 	OFS :1;   /* Offset bit                         */
	 unsigned char 	BSR0:1;   /* Bank select bit 0                  */
	 unsigned char 	BSR1:1;   /* Bank select bit 1                  */
	 unsigned char 	BSR2:1;   /* Bank select bit 2                  */
	 unsigned char 	 	:1;   /* Nothing assigned 					*/
	 unsigned char 		:1;   /* Nothing assigned  					*/
   } BIT;   		      	  /*       						    	*/
	 unsigned char BYTE;      /* Data bank register						*/
};

/*------------------------------------------------------
	Oscillation stop detection register //0x000C
------------------------------------------------------*/
union st_cm2 {                /* union CM2  	   					 */
   struct {              	  /* Bit  Access 		   				 */
	 unsigned char 	CM2_0:1;   /* Oscillation stop detection bit     */
	 unsigned char 	CM2_1:1;   /* Main clock switch bit              */
	 unsigned char 	CM2_2:1;   /* Oscillation stop detection status  */
	 unsigned char 	CM2_3:1;   /* Clock monitor bit                  */
	 unsigned char 	     :1;   /* Nothing assigned                   */
	 unsigned char 	     :1;   /* Nothing assigned                   */
	 unsigned char 	 	 :1;   /* Nothing assigned 					 */
	 unsigned char 	CM2_7:1;   /* Operation select bit(when an oscillation stop is detected) */
   } BIT;   		      	   /*       						    	*/
	 unsigned char BYTE;      /* Oscillation stop detection register						*/
};

/*------------------------------------------------------
   Watchdog timer control register //0x000f
-----------------------------------------------------*/
union st_wdc {               /* union WDC    	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char 	 B0:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B1:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B2:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char 	 B3:1;   /* High-order bit of watchdog timer	*/
     unsigned char 	 B4:1; 	 /* High-order bit of watchdog timer	*/
     unsigned char WDC5:1; 	 /* Cold start / warm start discrimination flag */
     unsigned char 	 B6:1; 	 /* Reserved bit, must always be 0		*/
     unsigned char WDC7:1;   /* Prescaler select bit				*/
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Watchdog timer control register     */

/*------------------------------------------------------
   Address match interrupt register 0 //0x0010
-----------------------------------------------------*/
union st_rmad0 {
   struct{
	unsigned char RMAD0L;     /* Address match interrupt register 0 low  8 bit */
	unsigned char RMAD0M;     /* Address match interrupt register 0 mid  8 bit */
	unsigned char RMAD0H;     /* Address match interrupt register 0 high 8 bit */
	unsigned char NC;         /* non use 					   */
   } BYTE;			  /* Byte access				   */
	unsigned long   DWORD;	  /* Word Access				   */
};				  /* Address match interrupt register 0 32 bit 	   */

/*------------------------------------------------------
   Address match interrupt register 1 //0x0014
-----------------------------------------------------*/
union st_rmad1 {
   struct{
	unsigned char RMAD1L;     /* Address match interrupt register 1 low  8 bit */
	unsigned char RMAD1M;     /* Address match interrupt register 1 mid  8 bit */
	unsigned char RMAD1H;     /* Address match interrupt register 1 high 8 bit */
	unsigned char NC;         /* non use 					   */
   } BYTE;			  /* Byte access		   		   */
   unsigned long   DWORD;	  /*	Word Access				   */
};				  /* Address match interrupt register 1 32 bit 	   */

/*------------------------------------------------------
   Voltage Detection Register 1 //0x0019
-----------------------------------------------------*/
union st_vcr1 {               /* union VCR1    	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char 	  B0:1;	 /* Reserved bit,must be 0          	*/
     unsigned char 	  B1:1;	 /* Reserved bit,must be 0          	*/
     unsigned char 	  B2:1;	 /* Reserved bit,must be 0          	*/
     unsigned char VC1_3:1;  /* Voltage down monitor flag           */
     unsigned char 	  B4:1;  /* Reserved bit,must be 0	            */
     unsigned char    B5:1;  /* Reserved bit,must be 0              */
     unsigned char 	  B6:1;  /* Reserved bit, must always be 0		*/
     unsigned char    B7:1;  /* Reserved bit,must be 0				*/
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Voltage Detection Register 1     */

/*------------------------------------------------------
   Voltage Detection Register 2 //0x001A
-----------------------------------------------------*/
union st_vcr2 {               /* union VCR2    	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char 	  B0:1;	 /* Reserved bit,must be 0          	*/
     unsigned char 	  B1:1;	 /* Reserved bit,must be 0          	*/
     unsigned char 	  B2:1;	 /* Reserved bit,must be 0          	*/
     unsigned char    B3:1;  /* Reserved bit,must be 0           */
     unsigned char 	  B4:1;  /* Reserved bit,must be 0	            */
     unsigned char    B5:1;  /* Reserved bit,must be 0              */
     unsigned char VC2_6:1;  /* Reset area monitor bit		*/
     unsigned char VC2_7:1;  /* Voltage down monitor bit			*/
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Voltage Detection Register 1     */

/*------------------------------------------------------
   Chip select expansion control register//0x001B
-----------------------------------------------------*/