?? oc8051_decoder.v
字號:
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_AJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = 2'bxx;
src_sel2 = 2'bxx;
alu_op = 4'bxxxx;
imm_sel = 2'bxx;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ADD_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ADDC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DEC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_INC_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOV_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOV_AR : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOV_DR : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOV_CR : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOV_RD : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ORL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_OR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_SUBB_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_XCH_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_RN;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XCH;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_XRL_R : begin
ram_rd_sel = `OC8051_RRS_RN;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_XOR;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
//op_code [7:1]
`OC8051_ADD_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ADDC_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_AC;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_I : begin
ram_rd_sel = `OC8051_RRS_I;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
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