?? oc8051_decoder.v
字號:
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_DD : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_DC : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_AND;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_AND;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_ANL_NB : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_RR;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_SUB;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CLR_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ACC;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CLR_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CLR_B : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CPL_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CPL_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b0;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_PSW;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CPL_B : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOT;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_RAM;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DA : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_DA;
wr = 1'b1;
psw_set = `OC8051_PS_CY;
cy_sel = `OC8051_CY_DC;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b1;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DEC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DEC_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DIV : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_B;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_RAM;
alu_op = `OC8051_ALU_DIV;
wr = 1'b1;
psw_set = `OC8051_PS_OV;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_D;
ram_wr_sel = `OC8051_RWS_D;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_SUB;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_INC_A : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_ACC;
src_sel1 = `OC8051_ASS_ACC;
src_sel2 = `OC8051_ASS_ZERO;
alu_op = `OC8051_ALU_ADD;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_1;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS?? 快捷鍵說明
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