/************************************************************************
 *									*
 *	Copyright (C) SEIKO EPSON CORP. 1999				*
 *									*
 *	File name: int.h						*
 *	  This is interrupt controller driver header file.		*
 *									*
 *	Revision history						*
 *		1999.03.11	T.Mineshima	Start.			*
 *		1999.04.22	T.Mineshima	Define modify.		*
 *									*
 ************************************************************************/

/* Address definition */
#define		INT_PP0_PP1_ADDR	0x40260		// Address for input0,1 port interrupt priority register
#define		INT_PP2_PP3_ADDR	0x40261		// Address for input2,3 port interrupt priority register
#define		INT_PK0_PK1_ADDR	0x40262		// Address for key input0,1 interrupt priority register
#define		INT_PHSD0_PHSD1_ADDR	0x40263		// Address for hih-speed DMA ch.0,1 interrupt priority register
#define		INT_PHSD2_PHSD3_ADDR	0x40264		// Address for hih-speed DMA ch.2,3 interrupt priority register
#define		INT_PDM_ADDR		0x40265		// Address for intelligent interrupt priority register
#define		INT_P16T0_P16T1_ADDR	0x40266		// Address for 16bit timer0,1 interrupt priority register
#define		INT_P16T2_P16T3_ADDR	0x40267		// Address for 16bit timer2,3 interrupt priority register
#define		INT_P16T4_P16T5_ADDR	0x40268		// Address for 16bit timer4,5 interrupt priority register
#define		INT_P8TM_PSIO0_ADDR	0x40269		// Address for 8bit timer and serial interface ch.0 interrupt priority register
#define		INT_PSIO1_PAD_ADDR	0x4026a		// Address for serial interface ch.1 and A/D converter interrupt priority register
#define		INT_PCTM_ADDR		0x4026b		// Address for clock timer interrupt priority register
#define		INT_PP4_PP5_ADDR	0x4026c		// Address for port input4,5 interrupt priority register
#define		INT_PP6_PP7_ADDR	0x4026d		// Address for port input6,7 interrupt priority register

#define		INT_EP0_EK_ADDR		0x40270		// Address for input port0-3 and key input0,1 interrupt enable register
#define		INT_EHDM_EIDM_ADDR	0x40271		// Address for HSDMA ch.0,1 and IDMA interrupt enable register
#define		INT_E16T0_E16T1_ADDR	0x40272		// Address for 16bit timer0,1 interrupt enable register
#define		INT_E16T2_E16T3_ADDR	0x40273		// Address for 16bit timer2,3 interrupt enable register
#define		INT_E16T4_E16T5_ADDR	0x40274		// Address for 16bit timer4,5 interrupt enable register
#define		INT_E8TU_ADDR		0x40275		// Address for 8bit timer0-3 interrupt enable register
#define		INT_ES_ADDR		0x40276		// Address for serial interface ch.0,1 receive error, receive buffer full, transmit buffer empty interrupt enable register
#define		INT_EADE_ECTM_EP4_ADDR	0x40277		// Address for A/D converter clock timer and input port 4-7 interrupt enable register

#define		INT_FP0_FK_ADDR		0x40280		// Address for input port0-3 and key input0,1 interrupt factor flag register
#define		INT_FHDM_FIDM_ADDR	0x40281		// Address for HSDMA ch.0,1 and IDMA interrupt factor flag register
#define		INT_F16T0_F16T1_ADDR	0x40282		// Address for 16bit timer0,1 interrupt factor flag register
#define		INT_F16T2_F16T3_ADDR	0x40283		// Address for 16bit timer2,3 interrupt factor flag register
#define		INT_F16T4_F16T5_ADDR	0x40284		// Address for 16bit timer4,5 interrupt factor flag register
#define		INT_F8TU_ADDR		0x40285		// Address for 8bit timer0-3 interrupt factor flag register
#define		INT_FS_ADDR		0x40286		// Address for serial interface ch.0,1 receive error, receive buffer full, transmit buffer empty interrupt factor flag register
#define		INT_FADE_FCTM_FP4_ADDR	0x40287		// Address for A/D converter clock timer and input port 4-7 interrupt factor flag register

#define		INT_RP0_RHDM_R16T0_ADDR	0x40290		// Address for input port0-3, HSDMA and 16bit timer0 IDMA request register
#define		INT_R16T1_R16T4_ADDR	0x40291		// Address for 16bit timer1-4 IDMA request register
#define		INT_R16T5_R8TU_RS0_ADDR	0x40292		// Address for 16bit timer5, 8bit timer0-3, serial interface ch.0 IDMA request register
#define		INT_RS1_RADE_RP4_ADDR	0x40293		// Address for serial interface ch.1, A/D converter, port input4-7 IDMA request register

#define		INT_RSTONLY_ADDR	0x4029f		// Address for interrupt factor flag reset method selection register


/* Bit field definition */
#define		INT_PRIH_LVL7		0x70		// Interrupt priority level 7 (high-order byte)
#define		INT_PRIH_LVL6		0x60		// Interrupt priority level 6 (high-order byte)
#define		INT_PRIH_LVL5		0x50		// Interrupt priority level 5 (high-order byte)
#define		INT_PRIH_LVL4		0x40		// Interrupt priority level 4 (high-order byte)
#define		INT_PRIH_LVL3		0x30		// Interrupt priority level 3 (high-order byte)
#define		INT_PRIH_LVL2		0x20		// Interrupt priority level 2 (high-order byte)
#define		INT_PRIH_LVL1		0x10		// Interrupt priority level 1 (high-order byte)
#define		INT_PRIH_LVL0		0x00		// Interrupt priority level 0 (high-order byte)

#define		INT_PRIL_LVL7		0x07		// Interrupt priority level 7 (low-order byte)
#define		INT_PRIL_LVL6		0x06		// Interrupt priority level 6 (low-order byte)
#define		INT_PRIL_LVL5		0x05		// Interrupt priority level 5 (low-order byte)
#define		INT_PRIL_LVL4		0x04		// Interrupt priority level 4 (low-order byte)
#define		INT_PRIL_LVL3		0x03		// Interrupt priority level 3 (low-order byte)
#define		INT_PRIL_LVL2		0x02		// Interrupt priority level 2 (low-order byte)
#define		INT_PRIL_LVL1		0x01		// Interrupt priority level 1 (low-order byte)
#define		INT_PRIL_LVL0		0x00		// Interrupt priority level 0 (low-order byte)

#define		INT_EK1			0x20		// Key input1 interrupt enable
#define		INT_EK0			0x10		// Key input0 interrupt enable
#define		INT_EP3			0x08		// Input port3 interrupt enable
#define		INT_EP2			0x04		// Input port2 interrupt enable
#define		INT_EP1			0x02		// Input port1 interrupt enable
#define		INT_EP0			0x01		// Input port0 interrupt enable
#define		INT_EIDMA		0x10		// IDMA interrupt enable
#define		INT_EHSDMA3		0x08		// HSDMA ch.3 interrupt enable
#define		INT_EHSDMA2		0x04		// HSDMA ch.2 interrupt enable
#define		INT_EHSDMA1		0x02		// HSDMA ch.1 interrupt enable
#define		INT_EHSDMA0		0x01		// HSDMA ch.0 interrupt enable
#define		INT_E16TC1		0x80		// 16bit timer1 comparison match A interrupt enable
#define		INT_E16TU1		0x40		// 16bit timer1 comparison match B interrupt enable
#define		INT_E16TC0		0x08		// 16bit timer0 comparison match A interrupt enable
#define		INT_E16TU0		0x04		// 16bit timer0 comparison match B interrupt enable
#define		INT_E16TC3		0x80		// 16bit timer3 comparison match A interrupt enable
#define		INT_E16TU3		0x40		// 16bit timer3 comparison match B interrupt enable
#define		INT_E16TC2		0x08		// 16bit timer2 comparison match A interrupt enable
#define		INT_E16TU2		0x04		// 16bit timer2 comparison match B interrupt enable
#define		INT_E16TC5		0x80		// 16bit timer5 comparison match A interrupt enable
#define		INT_E16TU5		0x40		// 16bit timer5 comparsion match B interrupt enable
#define		INT_E16TC4		0x08		// 16bit timer4 comparison match A interrupt enable
#define		INT_E16TU4		0x04		// 16bit timer4 comparsion match B interrupt enable
#define		INT_E8TU3		0x08		// 8bit timer3 underflow interrupt enable
#define		INT_E8TU2		0x04		// 8bit timer2 underflow interrupt enable