UHWORD	max_sl;		/* Maximum Silence period */
   UHWORD	sl_cnt;		/* Silence Counter */
   UHWORD	char1;		/* CONTROL char 1 */
   UHWORD	char2;		/* CONTROL char 2 */
   UHWORD	char3;		/* CONTROL char 3 */
   UHWORD	char4;		/* CONTROL char 4 */
   UHWORD	char5;		/* CONTROL char 5 */
   UHWORD	char6;		/* CONTROL char 6 */
   UHWORD	char7;		/* CONTROL char 7 */
   UHWORD	char8;		/* CONTROL char 8 */
   UHWORD	rccm;		   /* Rx Control Char Mask */
   UHWORD	rccr;		   /* Rx Char Control Register */
};


/*--------------------------------------------------------------------------*/
/*							IDMA parameter RAM								             */
/*--------------------------------------------------------------------------*/

struct idma_pram 

{
   UHWORD ibase;	    /* IDMA BD Base Address */
   UHWORD dcmr;       /* DMA Channel Mode Register */
   UWORD  sapr;       /* Source Internal Data Pointer */
   UWORD  dapr;       /* Destination Internal Data Pointer */
   UHWORD ibptr;      /* Buffer Descriptor Pointer */
   UHWORD write_sp;   /* No description given in manual */
   UWORD  s_byte_c;   /* Internal Source Byte Count */
   UWORD  d_byte_c;   /* Internal Destination Byte Count */
   UWORD  s_state;    /* Internal State */
   UWORD  itemp0;     /* Temp Data Storage */
   UWORD  itemp1;     /* Temp Data Storage */
   UWORD  itemp2;     /* Temp Data Storage */
   UWORD  itemp3;     /* Temp Data Storage */
   UWORD  sr_mem;     /* Data Storage for Peripherial Write */
   UHWORD read_sp;    /* No description given in manual */
   UHWORD nodesc0;    /* Diff Between Source and Destination Residue*/
   UHWORD nodesc1;    /* Temp Storage Address Pointer */
   UHWORD nodesc2;    /* SR_MEM Byte Count */
   UWORD  d_state;    /* Internal State */
};



/*--------------------------------------------------------------------------*/
/*   					RISC timer parameter RAM							             */
/*--------------------------------------------------------------------------*/

struct timer_pram 

{
   /*----------------------------*/
   /*	RISC timers parameter RAM */
   /*----------------------------*/

   UHWORD	tm_base;	   /* RISC timer table base adr */
   UHWORD	tm_ptr;		/* RISC timer table pointer */
   UHWORD	r_tmr;		/* RISC timer mode register */
   UHWORD	r_tmv;		/* RISC timer valid register */
   UWORD	   tm_cmd;		/* RISC timer cmd register */
   UWORD	   tm_cnt;		/* RISC timer internal cnt */
};


/*--------------------------------------------------------------------------*/
/*						ROM Microcode parameter RAM							          */
/*--------------------------------------------------------------------------*/

struct ucode_pram 

{
   /*---------------------------*/
   /*	RISC ucode parameter RAM */
   /*---------------------------*/

   UHWORD	rev_num;    /* Ucode Revision Number */
   UHWORD	d_ptr;		/* MISC Dump area pointer */
   UWORD	   temp1;		/* MISC Temp1 */
   UWORD	   temp2;		/* MISC Temp2 */
};


/*---------------------------------------------------------------------------*/
/* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */
/* Note that this area can also be used by microcodes and the QMC channel 	 */
/* specific parameter ram.													 */
/*---------------------------------------------------------------------------*/

struct user_data

{

   VUBYTE	udata_bd_ucode[0x200];	/* user data bd's or Ucode (small)  */
   VUBYTE	udata_bd_ucode2[0x200];	/* user data bd's or Ucode (medium) */
   VUBYTE	udata_bd_ucode3[0x400];	/* user data bd's or Ucode (large)  */
   VUBYTE	udata_bd[0x700];			/* user data bd's*/
   VUBYTE	ucode_ext[0x100];			/* Ucode Extension ram*/
   VUBYTE	RESERVED12[0x0c00];		/* Reserved area */

};



/***************************************************************************/
/*																		                     */
/*	Definitions of Embedded PowerPC (EPPC) internal memory structures,	   */
/*  including registers and dual-port RAM								            */
/*																		                     */
/***************************************************************************/

typedef struct eppc 

{
   /*-----------------------------------*/
   /* BASE + 0x0000: INTERNAL REGISTERS */
   /*-----------------------------------*/

   /*-----*/
   /* SIU */
   /*-----*/

   VUWORD	siu_mcr;		      /* module configuration reg */
   VUWORD	siu_sypcr;		   /* System protection cnt */
   UBYTE    RESERVED13[0x6];
   VUHWORD	siu_swsr;		   /* sw service */
   VUWORD	siu_sipend;		   /* Interrupt pend reg */
   VUWORD	siu_simask;		   /* Interrupt mask reg */
   VUWORD	siu_siel;		   /* Interrupt edge level mask reg */
   VUWORD	siu_sivec;		   /* Interrupt vector */
   VUWORD	siu_tesr;		   /* Transfer error status */
   VUBYTE	RESERVED14[0xc];  /* Reserved area */
   VUWORD	dma_sdcr;		   /* SDMA configuration reg */
   UBYTE    RESERVED15[0x4c];

   /*--------*/
   /* PCMCIA */
   /*--------*/

   VUWORD  pcmcia_pbr0;      /* PCMCIA Base Reg: Window 0 */
   VUWORD  pcmcia_por0;      /* PCMCIA Option Reg: Window 0 */
   VUWORD  pcmcia_pbr1;      /* PCMCIA Base Reg: Window 1 */
   VUWORD  pcmcia_por1;      /* PCMCIA Option Reg: Window 1 */
   VUWORD  pcmcia_pbr2;      /* PCMCIA Base Reg: Window 2 */
   VUWORD  pcmcia_por2;      /* PCMCIA Option Reg: Window 2 */
   VUWORD  pcmcia_pbr3;      /* PCMCIA Base Reg: Window 3 */
   VUWORD  pcmcia_por3;      /* PCMCIA Option Reg: Window 3 */
   VUWORD  pcmcia_pbr4;      /* PCMCIA Base Reg: Window 4 */
   VUWORD  pcmcia_por4;      /* PCMCIA Option Reg: Window 4 */
   VUWORD  pcmcia_pbr5;      /* PCMCIA Base Reg: Window 5 */
   VUWORD  pcmcia_por5;      /* PCMCIA Option Reg: Window 5 */
   VUWORD  pcmcia_pbr6;      /* PCMCIA Base Reg: Window 6 */
   VUWORD  pcmcia_por6;      /* PCMCIA Option Reg: Window 6 */
   VUWORD  pcmcia_pbr7;      /* PCMCIA Base Reg: Window 7 */
   VUWORD  pcmcia_por7;      /* PCMCIA Option Reg: Window 7 */
   VUBYTE  RESERVED16[0x20];  /* Reserved area */
   VUWORD  pcmcia_pgcra;     /* PCMCIA Slot A Control  Reg */
   VUWORD  pcmcia_pgcrb;     /* PCMCIA Slot B Control  Reg */
   VUWORD  pcmcia_pscr;      /* PCMCIA Status Reg */
   VUBYTE  RESERVED17[0x4];  /* Reserved area */
   VUWORD  pcmcia_pipr;      /* PCMCIA Pins Value Reg */
   VUBYTE  RESERVED18[0x4];  /* Reserved area */
   VUWORD  pcmcia_per;       /* PCMCIA Enable Reg */
   VUBYTE  RESERVED19[0x4];  /* Reserved area */

   /*------*/
   /* MEMC */
   /*------*/

   VUWORD	memc_br0;			/* base register 0 */
   VUWORD	memc_or0;			/* option register 0 */
   VUWORD	memc_br1;			/* base register 1 */
   VUWORD	memc_or1;			/* option register 1 */
   VUWORD	memc_br2;			/* base register 2 */
   VUWORD	memc_or2;			/* option register 2 */
   VUWORD	memc_br3;			/* base register 3 */
   VUWORD	memc_or3;			/* option register 3 */
   VUWORD	memc_br4;			/* base register 3 */
   VUWORD	memc_or4;			/* option register 3 */
   VUWORD	memc_br5;			/* base register 3 */
   VUWORD	memc_or5;			/* option register 3 */
   VUWORD	memc_br6;			/* base register 3 */
   VUWORD	memc_or6;			/* option register 3 */
   VUWORD	memc_br7;			/* base register 3 */
   VUWORD	memc_or7;			/* option register 3 */
   VUBYTE 	RESERVED20[0x24];	/* Reserved area */
   VUWORD	memc_mar;			/* Memory address */
   VUWORD	memc_mcr;			/* Memory command */
   VUBYTE	RESERVED21[0x4];	/* Reserved area */
   VUWORD	memc_mamr;			/* Machine A mode */
   VUWORD	memc_mbmr;			/* Machine B mode */
   VUHWORD	memc_mstat;			/* Memory status */
   VUHWORD	memc_mptpr;			/* Memory preidic timer prescalar */
   VUWORD	memc_mdr;			/* Memory data */
   VUBYTE	RESERVED22[0x80];	/* Reserved area */

   /*---------------------------*/
   /* SYSTEM INTEGRATION TIMERS */
   /*---------------------------*/

   VUHWORD	simt_tbscr;			/* Time base stat&ctr */
   VUBYTE	RESERVED23[0x2];	/* Reserved area */
   VUWORD	simt_tbreff0;		/* Time base reference 0 */
   VUWORD	simt_tbreff1;		/* Time base reference 1 */
   VUBYTE	RESERVED24[0x14];	/* Reserved area */
   VUHWORD	simt_rtcsc;			/* Realtime clk stat&cntr 1 */
   VUBYTE	RESERVED25[0x2];	/* Reserved area */
   VUWORD	simt_rtc;			/* Realtime clock */
   VUWORD	simt_rtsec;			/* Realtime alarm seconds */
   VUWORD	simt_rtcal;			/* Realtime alarm */
   VUBYTE	RESERVED26[0x10];	/* Reserved area */
   VUWORD	simt_piscr;			/* PIT stat&ctrl */
   VUWORD	simt_pitc;			/* PIT counter */
   VUWORD	simt_pitr;			/* PIT */
   VUBYTE	RESERVED27[0x34];	/* Reserved area */

   /*---------------*/
   /* CLOCKS, RESET */
   /*---------------*/
   
   VUWORD	clkr_sccr;			/* System clk cntrl */
   VUWORD	clkr_plprcr;		/* PLL reset&ctrl */
   VUWORD	clkr_rsr;			/* reset status */
   UBYTE    RESERVED28[0x74];	/* Reserved area */

   /*--------------------------------*/
   /* System Integration Timers Keys */
   /*--------------------------------*/

   VUWORD  simt_tbscrk;   		/* Timebase Status&Ctrl Key */
   VUWORD  simt_tbreff0k; 		/* Timebase Reference 0 Key */
   VUWORD  simt_tbreff1k; 		/* Timebase Reference 1 Key */
   VUWORD  simt_tbk;      		/* Timebase and Decrementer Key */
   UBYTE   RESERVED29[0x10];	/* Reserved area */
   VUWORD  simt_rtcsck;   		/* Real-Time Clock Status&Ctrl Key */

   VUWORD  simt_rtck;     		/* Real-Time Clock Key */
   VUWORD  simt_rtseck;   		/* Real-Time Alarm Seconds Key */
   VUWORD  simt_rtcalk;   		/* Real-Time Alarm Key */
   UBYTE   RESERVED30[0x10];	/* Reserved area */
   VUWORD  simt_piscrk;   		/* Periodic Interrupt Status&Ctrl Key */
   VUWORD  simt_pitck;    		/* Periodic Interrupt Count Key */
   UBYTE   RESERVED31[0x38];	/* Reserved area */
        
   /*----------------------*/
   /* Clock and Reset Keys */
   /*----------------------*/

   VUWORD  clkr_sccrk;    	      /* System Clock Control Key */
   VUWORD  clkr_plprcrk;  	      /* PLL, Low Power and Reset Control Key */
   VUWORD  clkr_rsrk;     		   /* Reset Status Key */
   UBYTE	  RESERVED32[0x4d4];	/* Reserved area */
              
   /*-----*/
   /* I2C */
   /*-----*/
   
   VUBYTE	i2c_i2mod;			/* i2c mode */
   UBYTE		RESERVED33[3];
   VUBYTE	i2c_i2add;			/* i2c address */
   UBYTE		RESERVED34[3];
   VUBYTE	i2c_i2brg;			/* i2c brg */
   UBYTE		RESERVED35[3];
   VUBYTE	i2c_i2com;			/* i2c command */
   UBYTE		RESERVED36[3];
   VUBYTE	i2c_i2cer;			/* i2c event */
   UBYTE		RESERVED37[3];
   VUBYTE	i2c_i2cmr;			/* i2c mask */
   VUBYTE	RESERVED38[0x8b];	/* Reserved area */

   /*-----*/
   /* DMA */
   /*-----*/

   VUBYTE	RESERVED39[0x4];	/* Reserved area */
   VUWORD	dma_sdar;			/* SDMA address reg */
   VUBYTE	RESERVED40[0x2];	/* Reserved area */
   VUBYTE	dma_sdsr;			/* SDMA status reg */
   VUBYTE	RESERVED41[0x3];	/* Reserved area */
   VUBYTE	dma_sdmr;			/* SDMA mask reg */
   VUBYTE	RESERVED42[0x1];	/* Reserved area */			   
   VUBYTE	dma_idsr1;			/* IDMA1 status reg */
   VUBYTE	RESERVED43[0x3];	/* Reserved area */
   VUBYTE	dma_idmr1;			/* IDMA1 mask reg */
   VUBYTE	RESERVED44[0x3];	/* Reserved area */
   VUBYTE	dma_idsr2;			/* IDMA2 status reg */
   VUBYTE	RESERVED45[0x3];	/* Reserved area */
   VUBYTE	dma_idmr2;			/* IDMA2 mask reg */
   VUBYTE	RESERVED46[0x13];	/* Reserved area */

   /*--------------------------*/
   /* CPM Interrupt Controller */
   /*--------------------------*/

   VUHWORD	cpmi_civr;			/* CP interrupt vector reg */
   VUBYTE	RESERVED47[0xe];	/* Reserved area */
   VUWORD	cpmi_cicr;			/* CP interrupt configuration reg */
   VUWORD	cpmi_cipr;			/* CP interrupt pending reg */
   VUWORD	cpmi_cimr;			/* CP interrupt mask reg */
   VUWORD	cpmi_cisr;			/* CP interrupt in-service reg */

   /*----------*/
   /* I/O port */
   /*----------*/

   VUHWORD	pio_padir;			/* port A data direction reg */
   VUHWORD	pio_papar;			/* port A pin assignment reg */
   VUHWORD	pio_paodr;			/* port A open drain reg */
   VUHWORD	pio_padat;			/* port A data register */
   VUBYTE	RESERVED48[0x8];	/* Reserved area */
   VUHWORD	pio_pcdir;			/* port C data direction reg */
   VUHWORD	pio_pcpar;			/* port C pin assignment reg */
   VUHWORD	pio_pcso;			/* port C special options */
   VUHWORD	pio_pcdat;			/* port C data register */
   VUHWORD	pio_pcint;			/* port C interrupt cntrl reg */
   UBYTE		RESERVED49[6];
   VUHWORD	pio_pddir;			/* port D Data Direction reg */
   VUHWORD	pio_pdpar;			/* port D pin assignment reg */
   UBYTE		RESERVED50[2];
   VUHWORD	pio_pddat;			/* port D data reg */