/*------------------------------*
 * Option Register Bank 3 (OR3) *
 *------------------------------*/

#define OR3_AM             0xFFFF8000   /* Address Mask */
#define OR3_ATM            0x00007000   /* Address Type Mask */
#define OR3_CSNT/SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR3_ACS/G5LA/G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR3_BI             0x00000100   /* Burst Inhibit */
#define OR3_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR3_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR3_TRLX           0x00000004   /* Timing Relaxed */
#define OR3_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED50         0x00000001



/*----------------------------*
 * Base Register Bank 4 (BR4) *
 *----------------------------*/

#define BR4_BA      0xFFFF8000   /* Base Address */
#define BR4_AT      0x00007000   /* Address Type */
#define BR4_PS      0x00000C00   /* Port Size */
#define BR4_PARE    0x00000200   /* Parity Enable */
#define BR4_WP      0x00000100   /* Write protect */
#define BR4_MS      0x000000C0   /* Machine Select */
#define RESERVED51  0x0000003E  
#define BR4_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 4 (OR4) *
 *------------------------------*/

#define OR4_AM             0xFFFF8000   /* Address Mask */
#define OR4_ATM            0x00007000   /* Address Type Mask */
#define OR4_CSNT/SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR4_ACS/G5LA/G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR4_BI             0x00000100   /* Burst Inhibit */
#define OR4_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR4_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR4_TRLX           0x00000004   /* Timing Relaxed */
#define OR4_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED52         0x00000001



/*----------------------------*
 * Base Register Bank 5 (BR5) *
 *----------------------------*/

#define BR5_BA      0xFFFF8000   /* Base Address */
#define BR5_AT      0x00007000   /* Address Type */
#define BR5_PS      0x00000C00   /* Port Size */
#define BR5_PARE    0x00000200   /* Parity Enable */
#define BR5_WP      0x00000100   /* Write protect */
#define BR5_MS      0x000000C0   /* Machine Select */
#define RESERVED53  0x0000003E  
#define BR5_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 5 (OR5) *
 *------------------------------*/

#define OR5_AM             0xFFFF8000   /* Address Mask */
#define OR5_ATM            0x00007000   /* Address Type Mask */
#define OR5_CSNT/SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR5_ACS/G5LA/G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR5_BI             0x00000100   /* Burst Inhibit */
#define OR5_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR5_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR5_TRLX           0x00000004   /* Timing Relaxed */
#define OR5_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED54         0x00000001



/*----------------------------*
 * Base Register Bank 6 (BR6) *
 *----------------------------*/

#define BR6_BA      0xFFFF8000   /* Base Address */
#define BR6_AT      0x00007000   /* Address Type */
#define BR6_PS      0x00000C00   /* Port Size */
#define BR6_PARE    0x00000200   /* Parity Enable */
#define BR6_WP      0x00000100   /* Write protect */
#define BR6_MS      0x000000C0   /* Machine Select */
#define RESERVED55  0x0000003E  
#define BR6_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 6 (OR6) *
 *------------------------------*/

#define OR6_AM             0xFFFF8000   /* Address Mask */
#define OR6_ATM            0x00007000   /* Address Type Mask */
#define OR6_CSNT/SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR6_ACS/G5LA/G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR6_BI             0x00000100   /* Burst Inhibit */
#define OR6_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR6_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR6_TRLX           0x00000004   /* Timing Relaxed */
#define OR6_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED56         0x00000001



/*----------------------------*
 * Base Register Bank 7 (BR7) *
 *----------------------------*/

#define BR7_BA      0xFFFF8000   /* Base Address */
#define BR7_AT      0x00007000   /* Address Type */
#define BR7_PS      0x00000C00   /* Port Size */
#define BR7_PARE    0x00000200   /* Parity Enable */
#define BR7_WP      0x00000100   /* Write protect */
#define BR7_MS      0x000000C0   /* Machine Select */
#define RESERVED57  0x0000003E  
#define BR7_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 7 (OR7) *
 *------------------------------*/

#define OR7_AM             0xFFFF8000   /* Address Mask */
#define OR7_ATM            0x00007000   /* Address Type Mask */
#define OR7_CSNT/SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR7_ACS/G5LA/G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR7_BI             0x00000100   /* Burst Inhibit */
#define OR7_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR7_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR7_TRLX           0x00000004   /* Timing Relaxed */
#define OR7_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED58         0x00000001



/*-------------------------------*
 * Memory Command Register (MCR) *
 *-------------------------------*/

#define MCR_OP        0xC0000000   /* Command Opcode */
#define RESERVED59    0x3F000000   
#define MCR_UM        0x00800000   /* User Machine */
#define RESERVED60    0x007F0000   
#define MCR_MB        0x0000E000   /* Memory Bank */
#define RESERVED61    0x00001000   
#define MCR_MCLF      0x00000F00   /* Memory Command Loop Field */
#define RESERVED62    0x000000C0   
#define MCR_MAD       0x0000003F   /* Machine Address */



/*--------------------------------*
 * Machine A Mode Register (MAMR) *
 *--------------------------------*/

#define MAMR_PTA         0xFF000000   /* Periodic Timer A Period */
#define MAMR_PTAE        0x00800000   /* Periodic Timer A Enable */
#define MAMR_AMA         0x00700000   /* Address Multiplex Size A */
#define RESERVED63       0x00080000   
#define MAMR_DSA         0x00060000   /* Disable Timer Period */
#define RESERVED64       0x00010000   
#define MAMR_G0CLA       0x0000E000   /* General Line 0 Control A */
#define MAMR_GPLA_A4DIS	 0x00001000   /* GPL_A4 Output Disable Line */
#define MAMR_RLFA        0x00000F00   /* Read Loop Field A */
#define MAMR_WLFA        0x000000F0   /* Write Loop Field A */
#define MAMR_TLFA        0x0000000F   /* Timer Loop Field A */ 



/*--------------------------------*
 * Machine B Mode Register (MBMR) *
 *--------------------------------*/

#define MBMR_PTB        0xFF000000   /* Periodic Timer B Period */
#define MBMR_PTBE       0x00800000   /* Periodic Timer B Enable */
#define MBMR_AMB        0x00700000   /* Address Multiplex Size B */
#define RESERVED65      0x00080000
#define MBMR_DSB        0x00060000   /* Disable Timer Period */
#define RESERVED66      0x00010000  
#define MBMR_G0CLB      0x0000E000   /* General Line 0 Control B */
#define MBMR_GPL_B4DIS	0x00001000   /* GPL_B4 Output Line Disable */
#define MBMR_RLFB       0x00000F00   /* Read Loop Field B */
#define MBMR_WLFB       0x000000F0   /* Write Loop Field B */
#define MBMR_TLFB       0x0000000F   /* Timer Loop Field B */



/*--------------------------------*
 * Memory Status Register (MSTAT) *
 *--------------------------------*/

#define MSTAT_PER0   0x8000   /* Parity Error Bank 0 */
#define MSTAT_PER1   0x4000   /* Parity Error Bank 1 */
#define MSTAT_PER2   0x2000   /* Parity Error Bank 2 */
#define MSTAT_PER3   0x1000   /* Parity Error Bank 3 */
#define MSTAT_PER4   0x0800   /* Parity Error Bank 4 */
#define MSTAT_PER5   0x0400   /* Parity Error Bank 5 */
#define MSTAT_PER6   0x0200   /* Parity Error Bank 6 */
#define MSTAT_PER7   0x0100   /* Parity Error Bank 7 */
#define MSTAT_WPER   0x0080   /* Write Protection Error */
#define RESERVED67   0x007F   




/*--------------------------------------------------*
 * Memory Periodic Timer Prescaler Register (MPTPR) *
 *--------------------------------------------------*/

#define MPTPR_PTP    0xFF00   /* Periodic Timers Prescaler */
#define RESERVED68   0x00FF	  



/*-------------------------------------------------------------------------*
 *                        SYSTEM INTEGRATION TIMERS 					   *
 *-------------------------------------------------------------------------*/


/*-----------------------------------------------------*
 * Timers Timebase Status and Control Register (TBSCR) *
 *-----------------------------------------------------*/

#define TBSCR_TBIRQ   0xFF00   /* Timebase Interrupt Request */
#define TBSCR_REFA    0x0080   /* Reference Interrupt Status */
#define TBSCR_REFB    0x0040   /* Reference Interrupt Status */
#define RESERVED69    0x0030  
#define TBSCR_REFAE   0x0008   /* Refernce Interrupt Enable */
#define TBSCR_REFBE   0x0004   /* Refernce Interrupt Enable */
#define TBSCR_TBF     0x0002   /* Timebase Freeze */
#define TBSCR_TBE     0x0001   /* Timebase Enable */



/*--------------------------------------------------------------------*
 * Timebase Reference Register 0 (TBREFF0)                            *
 *--------------------------------------------------------------------*
 * NOTE: There are two timebase reference registers (TBREFF0/TBREFF1) *
 *       associated with the lower part of the timebase. Each 		  *
 *		   register is 32-bits R/W. When there is a match between the *
 *		   contents of timebase and the reference register, a 		  *
 *		   maskable interrupt is generated. 					      *
 *--------------------------------------------------------------------*/

#define TBREFF0_TBREF   0xFFFFFFFF



/*-----------------------------------------*
 * Timebase Reference Register 1 (TBREFF1) *
 *-----------------------------------------*/

#define TBREFF1_TBREF   0xFFFFFFFF



/*-----------------------------------------------------*
 * Real-Time Clock Status and Control Register (RTCSC) *
 *-----------------------------------------------------*/

#define RTCSC_RTCIRQ    0xFF00   /* RTC Interrupt Request */
#define RTCSC_SEC       0x0080   /* Once Per Second Interrupt */
#define RTCSC_ALR       0x0040   /* Alarm Interrupt */
#define RESERVED70      0x0020  
#define RTCSC_38K       0x0010   /* Real_time Clock Source Select */
#define RTCSC_SIE       0x0008   /* Second interrupt Enable */
#define RTCSC_ALE       0x0004   /* Alarm Interrupt Enable */
#define RTCSC_RTF       0x0002   /* Real-Time Clock Freeze */
#define RTCSC_RTE       0x0001   /* Real-Time Clock Enable */



/*----------------------------------------------------------*
 * Real-Time Clock Register (RTC)                           *
 *----------------------------------------------------------*
 * NOTE: The real-time clock (RTC) register is a 32-bit R/W	*
 *       register. It contains the current value of the     *
 *		   real-time clock. 								*
 *----------------------------------------------------------*/

#define RTC_RTC   0xFFFFFFFF   



/*-----------------------------------------------------------*