?? masks860.h
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/*--------------------------------------------------------------*
* CP Interrupt Configuration Register (CICR) *
*--------------------------------------------------------------*
* NOTE: The 24-bit R/W CICR defines the request level for the *
* CPM interrupts, the priority between the SCCs, and the *
* highest priority interrupt. The CICR, which can be *
* dynamically changed the the user, is cleared at reset. *
*--------------------------------------------------------------*/
#define RESERVED94 0xFF000000
#define CICR_SDdP 0x00C00000 /* SCCd priority order */
#define CICR_SCcP 0x00300000 /* SCCc priority order */
#define CICR_SCbP 0x000C0000 /* SCCb priority order */
#define CICR_SCaP 0x00030000 /* SCCa priority order */
#define CICR_IRL0 0x00008000 /* Interrupt request level */
#define CICR_IRL1 0x00004000 /* Interrupt request level */
#define CICR_IRL2 0x00002000 /* Interrupt request level */
#define CICR_HP0 0x00001000 /* Highest priority */
#define CICR_HP1 0x00000800 /* Highest priority */
#define CICR_HP2 0x00000400 /* Highest priority */
#define CICR_HP3 0x00000200 /* Highest priority */
#define CICR_HP4 0x00000100 /* Highest priority */
#define RESERVED95 0x0000007E
#define CICR_SPS 0x00000001 /* Spread priority scheme */
/*-----------------------------------------------------------------*
* CP Interrupt Pending Register (CIPR) *
*-----------------------------------------------------------------*
* NOTE: Each bit in the 32-bit R/W CPM Interrupt Pending Register *
* (CIPR) corresponds to a CPM interrupt source. When a CPM *
* interrupt is received, the CPIC sets the corresponding *
* bit in the CIPR. This register is cleared at reset. *
* See MPC860 User's Manual. *
*-----------------------------------------------------------------*/
#define CIPR_PC15 0x80000000
#define CIPR_SCC1 0x40000000
#define CIPR_SCC2 0x20000000
#define CIPR_SCC3 0x10000000
#define CIPR_SCC4 0x08000000
#define CIPR_PC14 0x04000000
#define CIPR_TIMER1 0x02000000
#define CIPR_PC13 0x01000000
#define CIPR_PC12 0x00800000
#define CIPR_SDMA 0x00400000
#define CIPR_IDMA1 0x00200000
#define CIPR_IDMA2 0x00100000
#define RESERVED96 0x00080000
#define CIPR_TIMER2 0x00040000
#define CIPR_R-TT 0x00020000
#define CIPR_I2C 0x00010000
#define CIPR_PC11 0x00008000
#define CIPR_PC10 0x00004000
#define RESERVED97 0x00002000
#define CIPR_TIMER3 0x00001000
#define CIPR_PC9 0x00000800
#define CIPR_PC8 0x00000400
#define CIPR_PC7 0x00000200
#define RESERVED98 0x00000100
#define CIPR_TIMER4 0x00000080
#define CIPR_PC6 0x00000040
#define CIPR_SPI 0x00000020
#define CIPR_SMC1 0x00000010
#define CIPR_SMC2_PIP 0x00000008
#define CIPR_PC5 0x00000004
#define CIPR_PC4 0x00000002
#define RESERVED99 0x00000001
/*------------------------------------------------------------------*
* CP Interrupt Mask Register (CIMR) *
*------------------------------------------------------------------*
* NOTE: Each bit in the CIMR coresponds to a CPM interrupt source. *
* The user masks an interrupt by clearing the coresponding *
* bit in the CIMR and enables an interrupt by setting the *
* corresponding bit in the CIMR. When a masked CPM interrupt *
* occurs, the corresponding bit in the CIPR is still set, *
* regardless of the CIMR bit, but no interupt request is *
* passed to the CPU core. This register is cleared at reset. *
* See MPC860 User's Manual. *
*------------------------------------------------------------------*/
#define CIMR_PC15 0x80000000
#define CIMR_SCC1 0x40000000
#define CIMR_SCC2 0x20000000
#define CIMR_SCC3 0x10000000
#define CIMR_SCC4 0x08000000
#define CIMR_PC14 0x04000000
#define CIMR_TIMER1 0x02000000
#define CIMR_PC13 0x01000000
#define CIMR_PC12 0x00800000
#define CIMR_SDMA 0x00400000
#define CIMR_IDMA1 0x00200000
#define CIMR_IDMA2 0x00100000
#define RESERVED100 0x00080000
#define CIMR_TIMER2 0x00040000
#define CIMR_R-TT 0x00020000
#define CIMR_I2C 0x00010000
#define CIMR_PC11 0x00008000
#define CIMR_PC10 0x00004000
#define RESERVED101 0x00002000
#define CIMR_TIMER3 0x00001000
#define CIMR_PC9 0x00000800
#define CIMR_PC8 0x00000400
#define CIMR_PC7 0x00000200
#define RESERVED102 0x00000100
#define CIMR_TIMER4 0x00000080
#define CIMR_PC6 0x00000040
#define CIMR_SPI 0x00000020
#define CIMR_SMC1 0x00000010
#define CIMR_SMC2/PIP 0x00000008
#define CIMR_PC5 0x00000004
#define CIMR_PC4 0x00000002
#define RESERVED103 0x00000001
/*----------------------------------------------*
* CP Interrupt In-Service Register (CISR) *
*----------------------------------------------*
* NOTE: This register is cleared at reset. See *
* MPC860 User's Manual. *
*----------------------------------------------*/
#define CISR_PC15 0x80000000
#define CISR_SCC1 0x40000000
#define CISR_SCC2 0x20000000
#define CISR_SCC3 0x10000000
#define CISR_SCC4 0x08000000
#define CISR_PC14 0x04000000
#define CISR_TIMER1 0x02000000
#define CISR_PC13 0x01000000
#define CISR_PC12 0x00800000
#define CISR_SDMA 0x00400000
#define CISR_IDMA1 0x00200000
#define CISR_IDMA2 0x00100000
#define RESERVED104 0x00080000
#define CISR_TIMER2 0x00040000
#define CISR_R-TT 0x00020000
#define CISR_I2C 0x00010000
#define CISR_PC11 0x00008000
#define CISR_PC10 0x00004000
#define RESERVED105 0x00002000
#define CISR_TIMER3 0x00001000
#define CISR_PC9 0x00000800
#define CISR_PC8 0x00000400
#define CISR_PC7 0x00000200
#define RESERVED106 0x00000100
#define CISR_TIMER4 0x00000080
#define CISR_PC6 0x00000040
#define CISR_SPI 0x00000020
#define CISR_SMC1 0x00000010
#define CISR_SMC2/PIP 0x00000008
#define CISR_PC5 0x00000004
#define CISR_PC4 0x00000002
#define RESERVED107 0x00000001
/*-------------------------------------------------------------------------*
* INPUT/OUTPUT PORT *
*-------------------------------------------------------------------------*/
/*-------------------------------------------------------*
* Port A Data Direction Register (PADIR) *
*-------------------------------------------------------*
* NOTE: For each DRx bit, the definition is as follows: *
* *
* 0 = The corrsponding bit is an input. *
* *
* 1 = The corresponding bit is an output. *
* *
* This register is cleared at system reset. *
*-------------------------------------------------------*/
#define PADIR_DR0 0x8000
#define PADIR_DR1 0x4000
#define PADIR_DR2 0x2000
#define PADIR_DR3 0x1000
#define PADIR_DR4 0x0800
#define PADIR_DR5 0x0400
#define PADIR_DR6 0x0200
#define PADIR_DR7 0x0100
#define PADIR_DR8 0x0080
#define PADIR_DR9 0x0040
#define PADIR_DR10 0x0020
#define PADIR_DR11 0x0010
#define PADIR_DR12 0x0008
#define PADIR_DR13 0x0004
#define PADIR_DR14 0x0002
#define PADIR_DD15 0x0001
/*----------------------------------------------------------------*
* Port A Pin Assignment Register (PAPAR) *
*----------------------------------------------------------------*
* NOTE: For each DDx bit, the definition is as follows: *
* *
* 0 = General-purpose I/O. The peripheral functions *
* of the pin are not used. *
* *
* 1 = Dedicated peripheral function. The pin is used *
* by the internal module. The on-chip peripheral *
* function to which it is dedicated can be determined *
* by other bits such as those in the PADIR. *
* *
* This register is cleared at system reset. *
*----------------------------------------------------------------*/
#define PAPAR_DD0 0x8000
#define PAPAR_DD1 0x4000
#define PAPAR_DD2 0x2000
#define PAPAR_DD3 0x1000
#define PAPAR_DD4 0x0800
#define PAPAR_DD5 0x0400
#define PAPAR_DD6 0x0200
#define PAPAR_DD7 0x0100
#define PAPAR_DD8 0x0080
#define PAPAR_DD9 0x0040
#define PAPAR_DD10 0x0020
#define PAPAR_DD11 0x0010
#define PAPAR_DD12 0x0008
#define PAPAR_DD13 0x0004
#define PAPAR_DD14 0x0002
#define PAPAR_DD15 0x0001
/*---------------------------------------------------------------*
* Port A Open Drain Register (PAODR) *
*---------------------------------------------------------------*
* NOTE: For each ODx bit, the definition is as follows: *
* *
* 0 = The I/O pin is actively driven as an output. *
* *
* 1 = The I/O pin is an open-drain driver. As an output, *
* the pin is actively driven low, otherwise it is *
* three-stated. *
* *
* This register is cleared at system reset. *
*---------------------------------------------------------------*/
#define PAODR_OD9 0x0040
#define PAODR_OD10 0x0020
#define PAODR_OD11 0x0010
#define PAODR_OD12 0x0008
#define PAODR_OD14 0x0002
/*--------------------------------------------*
* Port A Data Register (PADAT) *
*--------------------------------------------*
* NOTE: This register is undefined at reset. *
* See MPC860 User's Manual. *
*--------------------------------------------*/
#define PADAT_D0 0x8000
#define PADAT_D1 0x4000
#define PADAT_D2 0x2000
#define PADAT_D3 0x1000
#define PADAT_D4 0x0800
#define PADAT_D5 0x0400
#define PADAT_D6 0x0200
#define PADAT_D7 0x0100
#define PADAT_D8 0x0080
#define PADAT_D9 0x0040
#define PADAT_D10 0x0020
#define PADAT_D11 0x0010
#define PADAT_D12 0x0008
#define PADAT_D13 0x0004
#define PADAT_D14 0x0002
#define PADAT_D15 0x0001
/*--------------------------------------------------------*
* Port C Data Direction Register (PCDIR) *
*--------------------------------------------------------*
* NOTE: When read, the Port C data (PCDAT) register *
* always reflects the current status of each line. *
*--------------------------------------------------------*/
#define RESERVED108 0xF000
#define PCDIR_DR4 0x0800
#define PCDIR_DR5 0x0400
#define PCDIR_DR6 0x0200
#define PCDIR_DR7 0x0100
#define PCDIR_DR8 0x0080
#define PCDIR_DR9 0x0040
#define PCDIR_DR10 0x0020
#define PCDIR_DR11 0x0010
#define PCDIR_DR12 0x0008
#define PCDIR_DR13 0x0004
#define PCDIR_DR14 0x0002
#define PCDIR_DR15 0x0001
/*------------------------------------------*
* Port C Pin Assignment Register (P?? 快捷鍵說明
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