#!/bin/csh -fif ( $# < 1 ) then    echo "First argument must be a top level module name!"    exitelse    set SIM_TOP = $1endifset current_par = 1set output_waveform = 0while ( $current_par < $# )    @ current_par = $current_par + 1    case wave:        @ output_waveform = 1        breaksw    default:        echo 'Unknown option "'$argv[$current_par]'"!'        exit        breaksw    endswendecho "-CDSLIB ../bin/cds.lib"          > ncvlog.argsecho "-HDLVAR ../bin/hdl.var"         >> ncvlog.argsecho "-MESSAGES"                      >> ncvlog.argsecho "-INCDIR ../../../bench/verilog" >> ncvlog.argsecho "-INCDIR ../../../rtl/verilog"   >> ncvlog.argsecho "-NOCOPYRIGHT"                   >> ncvlog.argsecho "-LOGFILE ../log/ncvlog.log"     >> ncvlog.argsecho "../../../bench/verilog/oc8051_tb.v                            " >> ncvlog.argsecho "../../../bench/verilog/oc8051_xram.v                          " >> ncvlog.argsecho "../../../bench/verilog/oc8051_uart_test.v                     " >> ncvlog.argsecho "../../../bench/verilog/oc8051_xrom.v                          " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_top.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_alu_src_sel.v                     " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_alu.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_decoder.v                         " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_divide.v                          " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_multiply.v                        " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_memory_interface.v                " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_ram_top.v                         " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_acc.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_comp.v                            " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_sp.v                              " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_dptr.v                            " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_cy_select.v                       " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_psw.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_indi_addr.v                       " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_ports.v                           " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_b_register.v                      " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_uart.v                            " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_int.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_tc.v                              " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_tc2.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_icache.v                          " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_wb_iinterface.v                   " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_sfr.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_rom.v                             " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_ram_256x8_two_bist.v              " >> ncvlog.argsecho "../../../rtl/verilog/oc8051_ram_64x32_dual_bist.v             " >> ncvlog.argsecho "../../../../common/generic_memories/rtl/verilog/generic_dpram.v" >> ncvlog.argsncvlog -f ncvlog.argsecho "-MESSAGES"                             > ncelab.argsecho "-NOCOPYRIGHT"                         >> ncelab.argsecho "-CDSLIB ../bin/cds.lib"               >> ncelab.argsecho "-HDLVAR ../bin/hdl.var"               >> ncelab.argsecho "-LOGFILE ../log/ncelab.log"           >> ncelab.argsecho "-SNAPSHOT worklib.bench:rtl"          >> ncelab.argsecho "-NO_TCHK_MSG"                         >> ncelab.argsecho "-ACCESS +RWC"                         >> ncelab.argsecho worklib.$SIM_TOP                       >> ncelab.argsncelab -f ncelab.argsecho "-MESSAGES"                   > ncsim.argsecho "-NOCOPYRIGHT"               >> ncsim.argsecho "-CDSLIB ../bin/cds.lib"     >> ncsim.argsecho "-HDLVAR ../bin/hdl.var"     >> ncsim.argsecho "-INPUT ncsim.tcl"           >> ncsim.argsecho "-LOGFILE ../log/ncsim.log"  >> ncsim.argsecho "worklib.bench:rtl"          >> ncsim.argsif ( $output_waveform ) then    echo "database -open waves -shm -into ../out/waves.shm"             > ./ncsim.tcl    echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl    echo "run"                                                         >> ./ncsim.tclelse    echo "run"  > ./ncsim.tclendifecho "quit" >> ncsim.tclncsim -LICQUEUE -f ./ncsim.args