/internal.do/1.1/Thu Jun  5 11:46:36 2003///make/1.8/Fri Jun 20 13:42:10 2003///make_fpga/1.1.1.1/Mon Jul 29 13:33:17 2002///make_verilog/1.7/Wed Apr  2 16:18:37 2003///oc8051_defines.v/1.4/Thu Jun  5 11:46:36 2003///oc8051_timescale.v/1.1.1.1/Mon Jul 29 13:33:17 2002///run/1.9/Mon Jun  9 15:51:31 2003///run_sim.scr/1.3/Fri Jun 20 13:42:10 2003///verilog.log/1.3/Mon Sep 30 15:24:14 2002//D