?? crt0.s
字號:
# Start-up function for an embedded environment
.file "crt0.c"
.text
.extern SIUIntr
.globl _start
.globl UpmTable
.globl UpmTableEnd
.align 2
#------------------------------------------------------------------------
# On-Chip Core Register Definitions
#------------------------------------------------------------------------
#
RomBase .equ 0x02000000
RamBase .equ 0x00000000
ICR .equ 148 # Interrupt Cause Register
ICTRL .equ 158 # Instruction Control Register
DER .equ 149 # Debug Enable Register
DPDR .equ 630 # Development Port Data Register
IMMR .equ 638 # Internal I/O base register
IC_CST .equ 560 # ICache Control Status Register
IC_ADR .equ 561 # ICache Address Register
IC_DAT .equ 562 # ICache Data Register
DC_CST .equ 568 # DCache Control Status Register
DC_ADR .equ 569 # DCache Address Register
DC_DAT .equ 570 # DCache Data Register
SIUMCR .equ 0x000 # SIU Module configuration
SYPCR .equ 0x004 # SIU System Protection Control
SWSR .equ 0x00E # Software service register
SIMASK .equ 0x014 # SI Mask Register
MCR .equ 0x168 # Memory Command
MAMR .equ 0x170 # Machine A Mode Register
MPTPR .equ 0x17A # Memory Periodic Timer Prescaler
MDR .equ 0x17C # Memory Data
BR0 .equ 0x100 # Base Register 0
OR0 .equ 0x104 # Option Register 0
BR1 .equ 0x108 # Base Register 1
OR1 .equ 0x10C # Option Register 1
BR2 .equ 0x110 # Base Register 2
OR2 .equ 0x114 # Option Register 2
BR3 .equ 0x118 # Base Register 3
OR3 .equ 0x11C # Option Register 3
BR4 .equ 0x120 # Base Register 4
OR4 .equ 0x124 # Option Register 4
BR5 .equ 0x128 # Base Register 5
OR5 .equ 0x12C # Option Register 5
PLPRCR .equ 0x284 # PLL, Low Power and Reset Control Reg
#------------------------------------------------------------------------
# LA macro - load a register with a word value
#------------------------------------------------------------------------
.macro LA reg,symbol
lis reg,%hiadj(symbol)
addi reg,reg,%lo(symbol)
.endm
#
#
#------------------------------------------------------------------------
# Instruction and Data Cache definition
# Note: must use with lis instruction to load into bit 0-15
#------------------------------------------------------------------------
#
CacheUnlockAllCmd .equ 0x0A00 # Cache Unlock_All command
CacheDisableCmd .equ 0x0400 # Cache Disable command
CacheInvAllCmd .equ 0x0C00 # Cache Invalidate_All command
CacheEnableCmd .equ 0x0200 # DCache_Enable Command
CacheEnableBit .equ 0x8000 # Cache Enable bit in I/DC_CST
#
#
# Speed of the CPU is 40mhz
# CHANGE THIS VALUE TO 0 for 25MHZ PARTS
#
TM_SPEED40 .equ 1
TM_DRAM70NS .equ 0
TM_DRAM60NS .equ 0
#------------------------------------------------------------------------
# SetCSReg macro - write a word to offset + r4
#------------------------------------------------------------------------
SetCSReg: macro data,offset
lis r3,%hi(data)
ori r3,r3,%lo(data)
stw r3,offset(r4)
endm
#
# INTERRUPT VECTORS
#
#
# RESERVED, UNUSED INTERRUPT
#
_Ires0:
.skip 256-(.-_Ires0)
#
# SYSTEM RESET
#
_reset:
addi r0,r0,0
_start:
# init stack pointer
addis r11,r0,__SP_INIT@ha
addi r1,r11,__SP_INIT@l
addis r13,r0,_SDA_BASE_@ha
addi r13,r13,_SDA_BASE_@l
addis r2,r0,_SDA2_BASE_@ha
addi r2,r2,_SDA2_BASE_@l
addi r0,r0,0
stwu r0,-64(r1)
#
# insert other init code here
#
# do rest in C
bl __init_main
# b exit
bl main # pull in main()
.skip 256-(.-_reset)
#
# MACHINE CHECK
#
_IMachineCheck:
rfi
.skip 256-(.-_IMachineCheck)
#
# DATA STORAGE
#
_IDataStore:
rfi
.skip 256-(.-_IDataStore)
#
# INSTRUCTION STORAGE
#
_IInstStore:
rfi
.skip 256-(.-_IInstStore)
#
# EXTERNAL INTERRUPT
#
_IExtInterrupt:
b SIUIntr
rfi
.skip 256-(.-_IExtInterrupt)
#
# ALIGNMENT
#
_IAlignment:
rfi
.skip 256-(.-_IAlignment)
#
# PROGRAM
#
_IProgram:
rfi
.skip 256-(.-_IProgram)
#
# FLOATING POINT (NOT USED ON 860)
#
_IFloat:
rfi
.skip 256-(.-_IFloat)
#
# DECREMENTER
#
_IDecrementer:
rfi
.skip 256-(.-_IDecrementer)
#
# RESERVED
#
.skip 512
#
# SYSTEM CALL
#
_ISystemCall:
rfi
.skip 256-(.-_ISystemCall)
#
# TRACE
#
_ITrace:
rfi
.skip 256-(.-_ITrace)
#
# FLOATING POINT ASSIST
#
_IFloatAssist:
rfi
.skip 512-(.-_IFloatAssist)
#
# SOFTWARE EMULATION
#
_ISoftEmulate:
rfi
.skip 256-(.-_ISoftEmulate)
#
# INSTRUCTION TBL MISS
#
_IInstTLB:
rfi
.skip 256-(.-_IInstTLB)
#
# DATA TBL MISS
#
_IDataTLB:
rfi
.skip 256-(.-_IDataTLB)
#
# INSTRUCTION TLB ERROR
#
_IInstTLBError:
rfi
.skip 256-(.-_IInstTLBError)
#
# DATA TLB ERROR
#
_IDataTLBError:
rfi
.skip 256-(.-_IDataTLBError)
#
# RESERVED
#
.skip 0x700
#
# DATA BREAKPOINT
#
_IDataBreak:
rfi
.skip 256-(.-_IDataBreak)
#
# INSTRUCTION BREAKPOINT
#
_IInstBreak:
rfi
.skip 256-(.-_IInstBreak)
#
# PERIPHERAL BREAKPOINT
#
_IPeripBreak:
rfi
.skip 256-(.-_IPeripBreak)
#
# NON-MASKABLE DEVELOPMENT PORT
#
_IDevPort:
rfi
.skip 256-(.-_IDevPort)
# Init Code
# Do the rest in "C"
.section .init,2,C
.globl __init
.align 2
__init:
mfspr r0,8
stwu r1,-64(r1)
stw r0,68(r1)
.section .fini,2,C
# Return from __init
lwz r0,68(r1)
addi r1,r1,64
mtspr 8,r0
blr
.globl __fini
__fini:
mfspr r0,8
stwu r1,-64(r1)
stw r0,68(r1)
.section .eini,2,C
# Return from __fini
lwz r0,68(r1)
addi r1,r1,64
mtspr 8,r0
blr
# MPC860 Init Code
# Do the rest in "C"
.section .tfInit860,2,C
.globl __tfInit860
.globl UpmTable
.globl UpmTableEnd
.align 2
__tfInit860:
#
# Atlas Communications Engines
# DARWIN INITIALIZATION (MPC860 Board)
# You will need to modify four your hardware
# "C" Syntax:
# void init860(unsigned long immrValue);
#
#save IMMR in r4
mr r4,r3
mtspr IMMR,r3
#------------------------------------------------------------------------
# Disable Data Cache before accesing any more registers
# Save the status of DC_CST in R8 for the flush routine
#------------------------------------------------------------------------
mfspr r3,DC_CST
ori r8,r3,0 # save DC_CST in r8
lis r3,0x0400 # DCache Disable command
mtspr DC_CST,r3
#------------------------------------------------------------------------
# Set the decrementer to a very high value
#------------------------------------------------------------------------
lis r3,0x7FFF
addi r3,r3,0xFFFF
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