unsigned int  code PanelFactor[][8]={
//Hsize , Vsize , Hwid , HBpor , HFpor , Vwid , VFpor , VBpor
 {1024  ,  768  ,  16  ,   32  ,  32   ,  10  ,  10   ,  10,  },//LG15
 {1280  , 1024  ,  16  ,   32  ,  32   ,  10  ,  10   ,  10,  },//CM17
 {1280  ,  768  ,  82  ,  200  , 180   ,  10  ,  15   ,  30,  },//WXGA
 {1280  , 1024  , 116  ,  132  , 132   ,  10  ,  10   ,  10,  },//AU17
 {1280  , 1024  ,  38  ,  248  , 112   ,  48  ,   3   ,  10,  },//SM17
};
/////////////////////////////////////////////////////////////////////////////////////////////////
unsigned char code PanelControl[][17]={
{//LG15
  1,	// PCLK0 invert("1"=invert)
  2,	// PCLK0 output phase delay(0~7)
  0,	// PCLK1 invert("1"=invert)
  0,	// PCLK1 output phase delay(0~7)
  0,	// Pixel output format(0/1:Single/Dual)
  0,	// Pixel Swap("0"=[23:0] are even/1st pixel)
  0,	// Hsync Polarity("0"=active low)
  0,	// Vsync Polarity("0"=active low)
  1,	// DE Polarity("0"=active low)
  8,	// Data bus driving strength
  8,	// Clock0 output driving strength
  8,	// Clock1 output driving strength
  0,	// (0/1:6-bit/8-bit panel)
  1,	// Dithering Enable
  0,    // Dual port parallel format enable
  0x08, // PLL Coarse Gain
  1     // Tcon function enable(1:not enable)
 },
{//CM17
  0,	// PCLK0 invert("1"=invert)
  0,	// PCLK0 output phase delay(0~7)
  0,	// PCLK1 invert("1"=invert)
  0,	// PCLK1 output phase delay(0~7)
  1,	// Pixel output format(0/1:Single/Dual)
  //1,	// Pixel Swap("0"=[23:0] are even/1st pixel)//狾