//testbench for vgasdram`timescale 1ns/1nsmodule tb_sdrtest;/*sdram	sd_model(				.clk(sdram_clk),				.csb(sdram_cs_n), 				.cke(sdram_cke), 				.ba(sdram_ba), 				.ad(sdram_addr), 				.rasb(sdram_ras_n), 				.casb(sdram_cas_n), 				.web(sdram_we_n), 				.dqm(2'b00), 				.dqi(sdram_data)				);*///print_task.v里包含常用信息打印任務封裝print_task	print();//sys_ctrl_task.v里包含系統時鐘產生單元和系統復位任務sys_ctrl_task	sys_ctrl(						.clk(clk),						.rst_n(rst_n)					);						//input				//wire clk;		//系統時鐘,25MHz//wire rst_n;		//復位信號，低電平有效	//output	// FPGA與SDRAM硬件接口wire sdram_clk;				// SDRAM時鐘信號wire sdram_cke;				// SDRAM時鐘有效信號wire sdram_cs_n;			// SDRAM片選信號wire sdram_ras_n;			// SDRAM行地址選通脈沖wire sdram_cas_n;			// SDRAM列地址選通脈沖wire sdram_we_n;			// SDRAM寫允許位wire[1:0] sdram_ba;			// SDRAM的L-Bank地址線wire[11:0] sdram_addr;		// SDRAM地址總線wire rs232_tx;				// 串口數據發送//inoutwire[15:0] sdram_data;		// SDRAM數據總線////////////////////////////////////////////////	// SDRAM的封裝接口測試引出/*wire sdram_rd_ack;		//系統讀SDRAM響應信號	wire sdram_wr_ack;wire[15:0] sys_data_in;wire[15:0] sys_data_out;	//讀SDRAM時數據暫存器,(格式同上)wire sdram_busy;			// SDRAM忙標志，高表示SDRAM處于工作中wire sys_dout_rdy;			// SDRAM數據輸出完成標志wire[15:0] rdf_dout;		//sdram數據讀出緩存FIFO輸出數據總線	wire rdf_rdreq;			//sdram數據讀出緩存FIFO數據輸出請求，高有效*/////////////////////////////////////////////////sdr_test	sd(			.clk(clk),			.rst_n(rst_n),			.sdram_clk(sdram_clk),			.sdram_cke(sdram_cke),			.sdram_cs_n(sdram_cs_n),			.sdram_ras_n(sdram_ras_n),			.sdram_cas_n(sdram_cas_n),			.sdram_we_n(sdram_we_n),			.sdram_ba(sdram_ba),			.sdram_addr(sdram_addr),			.sdram_data(sdram_data),			.rs232_tx(rs232_tx)/*,			.sdram_rd_req(sdram_rd_req),			.sdram_wr_ack(sdram_wr_ack),			.sdram_rd_ack(sdram_rd_ack),			.sys_data_in(sys_data_in),			.sys_data_out(sys_data_out),			.sdram_busy(sdram_busy),			.sys_dout_rdy(sys_dout_rdy),			.rdf_dout(rdf_dout),			.rdf_rdreq(rdf_rdreq)*/		);reg[15:0] sdram_datar;reg sdatalink;				assign sdram_data = sdatalink ? sdram_datar:16'hzzzz;integer write_232rx_file;	//定義文件指針	integer cnt512;			//512計數initial begin		//串口數據接收文件初始化	write_232rx_file = $fopen("write_232rx_file.txt");//txt文件初始化	$fdisplay(write_232rx_file,"rx232 receive data display:\n");	cnt512 = 0;	sdatalink = 0;		//SDRAM輸入接口初始化	//sdatalink = 0;		//系統復位	sys_ctrl.sys_reset(400);	//有效復位400ns	#200_000;	//等待200us	//sdram_wr_task;	#20_000;	//等待30us	//sdram_rd_task;		//等待，系統測試完成	#30_000_000;		//等待30ms		print.terminate;		end//模擬sdram存儲寫入數據reg[15:0] memd[255:0];	//256個16bit緩存integer cnt;always @(posedge sdram_clk) begin	if({sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} == 5'b10011) begin	//行選通		@(posedge sdram_clk); 		@(posedge sdram_clk); 		if({sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} == 5'b10100) begin	//寫命令			for(cnt=0;cnt<256;cnt=cnt+1) begin				memd[cnt] = sdram_data;				@(posedge sdram_clk);			end			end	endend//模擬sdram在數據讀時將數據送出integer cntrd;always @(posedge sdram_clk) begin	if({sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} == 5'b10011) begin	//行選通		@(posedge sdram_clk); 		@(posedge sdram_clk); 		if({sdram_cke,sdram_cs_n,sdram_ras_n,sdram_cas_n,sdram_we_n} == 5'b10101) begin	//讀命令			@(posedge sdram_clk); 			@(posedge sdram_clk); 			sdatalink = 1'b1;			for(cntrd=0;cntrd<256;cntrd=cntrd+1) begin				#5;				sdram_datar = memd[cntrd];				@(posedge sdram_clk);			end			@(posedge sdram_clk);			sdatalink = 1'b0;			end	endend//模擬串口接收integer cntbit;		reg[7:0] rxdata;	//串口接收數據寄存器parameter	BPS9600		= 104_167;		//9600bps傳輸率parameter	BPS9600_2	= 52_083;		//9600bps傳輸率always @(negedge rs232_tx) begin	if(!rs232_tx) begin		#BPS9600;		//起始位等待		#BPS9600_2;		//對齊數據中間		for(cntbit=0;cntbit<8;cntbit=cntbit+1) begin	//采樣8bit數據			rxdata[cntbit] = rs232_tx;			#BPS9600;		//等待下一位		end		if(!rs232_tx) print.error("rs232_tx stop bit error");	//結束位出錯報告		else #BPS9600_2;		//等待結束位完成		$fdisplay(write_232rx_file,"Receive data %d  :  %d\n",cnt512,rxdata);		//將當前接收到的串口數據輸出到write_232rx_file.txt中		$write("current receive data is %d\n",rxdata);		cnt512 = cnt512+1;	end	endendmodule