?? bsestart.s
字號:
#
# bsestart.s
#
# Barnett Systems Engineering
# MPC823 Poweron Reset Initialization Assembly Source File
#
# Author: Harry E. Barnett 9/27/99
# harryb@hbbse.com http://www.hbbse.com
#
# Version V1.00
#
#########################################################################
.list
.file "bsestart.s"
.title "BSE MPC823 Poweron Reset Init Assembly Source File"
.text
.align 2
# PPC register equivalents
rTOC .equ 2
XRTOC .equ 20
# Memory Mapped Register Offsets
CS_BR0 .equ 0x100
CS_BR1 .equ 0x108
CS_BR2 .equ 0x110
CS_BR4 .equ 0x120
CS_OR0 .equ 0x104
CS_OR1 .equ 0x10C
CS_OR2 .equ 0x114
CS_OR4 .equ 0x124
MAMR .equ 0x170
MAR .equ 0x164
MBMR .equ 0x174
MCR .equ 0x168
MDR .equ 0x17C
MPTPR .equ 0x17A
PISCR .equ 0x240
PISCRK .equ 0x340
PLPRCR .equ 0x284
PLPRCRK .equ 0x384
RTC .equ 0x224
RTCAL .equ 0x22C
RTCALK .equ 0x32C
RTCK .equ 0x324
RTCSC .equ 0x220
RTCSCK .equ 0x320
RTSEC .equ 0x228
RTSECK .equ 0x328
SCCR .equ 0x280
SCCRK .equ 0x380
SIUMCR .equ 0x000
SYPCR .equ 0x004
TBSCR .equ 0x200
TBSCRK .equ 0x300
# Initializations
# SRN
# CS0,CS1 -> FLASH; CS2 -> SDRAM
#CS_BR0_INIT .equ 0x40000801
#CS_BR1_INIT .equ 0x40200801
#CS_BR2_INIT .equ 0x00000081
#CS_OR0_INIT .equ 0xFFE00160
#CS_OR1_INIT .equ 0xFFE00160
#CS_OR2_INIT .equ 0xFF000A00
CS_BR0_INIT .equ 0x00000801
CS_BR1_INIT .equ 0x00200801
CS_BR2_INIT .equ 0xff000081
CS_OR0_INIT .equ 0xFFE00160
CS_OR1_INIT .equ 0xFFE00160
CS_OR2_INIT .equ 0xFF000A00
DC_DISABLE .equ 0x04000000
DC_ENABLE .equ 0x02000000
DEC_INIT_MAX .equ 0x7FFFFFFF
# srn
# Change for New Vec location
MSR_INIT .equ 0x00009042
MSR_INIT_NO_EE .equ 0x00001042
DER_INIT .equ 0xFDC3400F
ICTRL_INIT .equ 0x00000007
IC_DISABLE .equ 0x04000000
IC_ENABLE .equ 0x02000000
IMMR_INIT .equ 0x80000000
TEMP_STACK .equ 0x80002ff0
KEY_UNLOCK .equ 0x55CCAA33
# srn 04.06.27
# SCCR.RTDIV=0, RT-clk divided by 4
# SCCR.RTSEL=0, select OSCM
SCCR_INIT .equ 0x01000000
# SRN
# INIT VALUE OF HHPPC'SDRAM (SEE mpc.init)
MAMR_INIT .equ 0xD0802114
MAR_UPMA_INIT .equ 0x00000088
MCR_UPMA_SETUP_INIT .equ 0x80004105
MCR_UPMA_REFRESH_INIT .equ 0x80004830
MCR_UPMA_LAST_INIT .equ 0x80004106
MCR_UPMA_WRITE_INIT .equ 0x00004000
MPTPR_INIT .equ 0x0400
PISCR_INIT .equ 0x0082
# srn 04.06.27
# GCLK = (9 + 1) * 5MHz = 50MHz
PLPRCR_INIT .equ 0x0090C000
RTCAL_INIT .equ 0xFFFFFFFF
RTCSC_INIT .equ 0x00D3
RTC_INIT .equ 0x00000000
RTSEC_INIT .equ 0xFFFFFFFF
SIUMCR_INIT .equ 0x00012440
SYPCR_INIT .equ 0xFFFFFF88
TBSCR_INIT .equ 0x00C3
# END OF DEFINE
# GLOBALS
.global poreset # start of system code
.extern DECIntr
.extern _start
.entry poreset
.text
.align 2
# SRN
# 07.23
#
# ADD FOR BURN FLASH
.org (0x00000000)
.string "2004.07.23"
# System Reset entry point: Offset 0x100
.org (0x00000100)
poreset:
b bsestart
# Decrementer exception entry point 0x900
.org (0x00000900)
dec_exc:
b DECIntr
# System Call exception entry point 0xC00
.org (0x00000C00)
sc_exc:
b OSCtxSw
.org (0x00000D00)
trace_exc:
b .
.org (0x00000E00)
b .
.org (0x00001000)
b .
.org (0x00001100)
rfi
.org (0x00001200)
rfi
.org (0x00001300)
rfi
.org (0x00001400)
rfi
.org (0x00001C00)
b .
.org (0x00001D00)
b .
.org (0x00001E00)
b .
.org (0x00001F00)
b .
##################################
#
# START OF INITIALIZATION
#
##################################
# Spotty chip initialization for the moment
# .org 0x40003000
# ASSIGNED BY LINKER COMMAND FILE
.text
bsestart:
################################
#
# Init Temp Stack first
#
################################
lis r1, TEMP_STACK@h
ori r1, r1, TEMP_STACK@l
################################
# Setup Unlock Key register r5: r5 is reserved from here to end of module
lis r5, KEY_UNLOCK@h
ori r5, r5, KEY_UNLOCK@l
SPR_Init:
# Initialize MSR and SRR1
lis r12, MSR_INIT_NO_EE@h
ori r12, r12, MSR_INIT_NO_EE@l
mtmsr r12
mtspr SRR1, r12
# Initialize Instruction Support Control Register
lis r12, ICTRL_INIT@h
ori r12, r12, ICTRL_INIT@l
mtspr ICTRL, r12
# Initialize Debug Enable Register
lis r12, DER_INIT@h
ori r12, r12, DER_INIT@l
mtspr DER, r12
# Initialize Decrementer Register
lis r12, DEC_INIT_MAX@h
ori r12, r12, DEC_INIT_MAX@l
mtspr DEC, r12
# Initialize Interrupt Cause Register
# clear all interrupt causes by reading the ICR
mfspr r12, ICR
IMMR_Init:
# Initialize the IMMR register
# r4 is reserved from here to end of module
lis r4, IMMR_INIT@h
mtspr IMMR, r4 # initialize the IMMR register
mfspr r4, IMMR # read it back
rlwinm r4, r4, 0, 0, 15 # only high 16 bits count
ClockInit:
# Initialize System Clock Control Register
stw r5, SCCRK(r4) # Unlock
lis r12, SCCR_INIT@h
ori r12, r12, SCCR_INIT@l
stw r12, SCCR(r4)
# Initialize the PLL, Low Power, and Reset Control Register
stw r5, PLPRCRK(r4) # Unlock
lis r12, PLPRCR_INIT@h
ori r12, r12, PLPRCR_INIT@l
stw r12, PLPRCR(r4)
SIU_Init:
# Initialize SIU Module Configuration Register
lis r12, SIUMCR_INIT@h
ori r12, r12, SIUMCR_INIT@l
stw r12, SIUMCR(r4)
# Initialize the System Protection Control Register
lis r12, SYPCR_INIT@h
ori r12, r12, SYPCR_INIT@l
stw r12, SYPCR(r4)
SI_TimersInit:
# Initialize the Time Base Status and Control register
stw r5, TBSCRK(r4) # Unlock
li r12, TBSCR_INIT
sth r12, TBSCR(r4)
# Initialize Real Time Clock Register
stw r5, RTCK(r4) # Unlock
lis r12, RTC_INIT@h
ori r12, r12, RTC_INIT@l
stw r12, RTC(r4)
# Initialize Real Time Clock Status and Control Register
stw r5, RTCSCK(r4) # Unlock
li r12, RTCSC_INIT
sth r12, RTCSC(r4)
# Initialize Real Time Clock Alarm Register
stw r5, RTCALK(r4) # Unlock
lis r12, RTCAL_INIT@h
ori r12, r12, RTCAL_INIT@l
stw r12, RTCAL(r4)
# Initialize Real Time Clock Alarm Seconds Register
stw r5, RTSECK(r4) # Unlock
lis r12, RTSEC_INIT@h
ori r12, r12, RTSEC_INIT@l
stw r12, RTSEC(r4)
# Check...
lwz r12,RTSEC(r4)
# Initialize Periodic Interrupt Status and Control Register
stw r5, PISCRK(r4) # Unlock
li r12, PISCR_INIT
sth r12, PISCR(r4)
MEMC_Init:
# program BR0
lis r12, CS_BR0_INIT@h
ori r12, r12, CS_BR0_INIT@l
stw r12, CS_BR0(r4)
# program OR0
lis r9, CS_OR0_INIT@h
ori r9, r9, CS_OR0_INIT@l
stw r9, CS_OR0(r4)
# program OR1
lis r9, CS_OR1_INIT@h
ori r9, r9, CS_OR1_INIT@l
stw r9, CS_OR1(r4)
# program BR1
lis r12, CS_BR1_INIT@h
ori r12, r12, CS_BR1_INIT@l
stw r12, CS_BR1(r4)
# Initialize UPMA (SDRAM)
UPMASetup:
# Set up for 50 MHz clock commands
lis r12, UPMATable_50End@ha
ori r12, r12, UPMATable_50End@l
la r9, 0(r12)
lis r12, UPMATable_50@ha
ori r12, r12, UPMATable_50@l
la r12, 0(r12)
sub r9, r9, r12 # compute table size
srawi r9, r9, 2 # in words
mtctr r9 # set up counter
subi r12, r12, 4 # set up pointer to table
# program MCR with initial write command
lis r9, MCR_UPMA_WRITE_INIT@h
ori r9, r9, MCR_UPMA_WRITE_INIT@l
UPMAInit:
lwzu r8, 4(r12) # get data from table
stw r8, MDR(r4) # store data to MD register
stw r9, MCR(r4) # issue write command to MCR register
addi r9, r9, 1 # update UPMB address in write command
bdnz UPMAInit
# Make SDRAM Ready
# Initialize Memory Periodic Timer Prescalar Register, MPTPR
li r12, MPTPR_INIT
sth r12, MPTPR(r4)
# Initialize Machine A Mode Register, MAMR, 4 beats
lis r12, MAMR_INIT@h
ori r12, r12, MAMR_INIT@l
stw r12, MAMR(r4)
# Map CS2 to SDRAM
# program OR2
lis r12, CS_OR2_INIT@h
ori r12, r12, CS_OR2_INIT@l
stw r12, CS_OR2(r4)
# program BR2
lis r12, CS_BR2_INIT@h
ori r12, r12, CS_BR2_INIT@l
stw r12, CS_BR2(r4)
# program MAR
lis r12, MAR_UPMA_INIT@h
ori r12, r12, MAR_UPMA_INIT@l
stw r12, MAR(r4)
# program MCR with setup
lis r12, MCR_UPMA_SETUP_INIT@h
ori r12, r12, MCR_UPMA_SETUP_INIT@l
# run setup
stw r12, MCR(r4)
# program MCR with execute refresh
lis r12, MCR_UPMA_REFRESH_INIT@h
ori r12, r12, MCR_UPMA_REFRESH_INIT@l
# run refresh
stw r12, MCR(r4)
# program MCR last
lis r12, MCR_UPMA_LAST_INIT@h
ori r12, r12, MCR_UPMA_LAST_INIT@l
# run last
stw r12, MCR(r4)
#SDRAM is now ready to use
UPMBProgramEnd:
# End
CacheDisable:
# Disable the instruction/data cache
lis r12, IC_DISABLE@h # load disable cmd
ori r12, r12,IC_DISABLE@l
isync
mtspr IC_CST, r12 # disable I cache
lis r12, DC_DISABLE@h # load disable cmd
ori r12, r12, DC_DISABLE@l
sync
mtspr DC_CST, r12 # disable D cache
# initialize the stack pointer, just in case
init_stack:
lis r1,__SP_INIT@h
ori r1,r1,__SP_INIT@l
addi r1,r1,-0x20
# END OF INITIALIZATION
# GO TO bsecrt0.s
######### Test ############################
#bl SetLed
######### End ############################
b _start
# Should never get here, but in case we do...
poststart:
b poststart
nop
nop
nop
# UPMA setup for HHPPC860 16 MB SDRAM
# for clocks 32-50 MHz
UPMATable_50:
# single read. (offset 0x0 in UPM RAM)
.long 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00
.long 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
# burst read. (offset 0x8 in UPM RAM)
.long 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
.long 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# single write. (offset 0x18 in UPM RAM)
.long 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# burst write. (offset 0x20 in UPM RAM)
.long 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
.long 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# refresh. (offset 0x30 in UPM RAM)
.long 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff
.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
# exception. (offset 0x3c in UPM RAM)
.long 0x7ffffc07, 0xffffffff, 0xffffffff, 0xffffffff
#end of MPC823FADS UPMB programming
UPMATable_50End:
.end
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