?? smbdesc.def
字號(hào):
; left-hand-side key word to describe: ;
; Processor Type ;
;-----------------------------------------------------------------------;
;-----------------;
; PROCESSOR FAMILY;
;-----------------;-----------------------------------------------------;
; Processor Family is a runtime information. During POST ;
; it will return the correct family. ;
;-----------------------------------------------------------------------;
;------------------------------;
; PROCESSOR UPGRADE INFORMATION;
;------------------------------;----------------------------------------;
; Following enumerates describes Processor Upgrade. At ;
; any given time only one value can be selected. Use ;
; left-hand-side key word to describe: ;
; Processor Upgrade Information ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
; UPG_OTHER...................... Other ;
; UPG_UNKNOWN.................... Unknown ;
; UPG_DAUGHTER_BOARD............. Daughter Board ;
; UPG_ZIF_SOCKET................. ZIF Socket ;
; UPG_REPLACEABLE_PIGGY_BACK..... Replaceable Piggyback ;
; UPG_NONE....................... None ;
; UPG_LIF_SOCKET................. Lif Socket ;
; UPG_SLOT1...................... Slot1 ;
; UPG_SLOT2...................... Slot2 ;
; UPG_S370....................... Socket 370 ;
;-----------------------------------------------------------------------;
;Processor general info:
;-----------------------
PROCESSOR_INFO = Present
NUMBER_OF_PROCESSOR = 1
PROCESSOR_INFO_1 DEFINE <Socket 7, 300MHz, UPG_S370>
PROCESSOR_VOLTAGE_1 DEFINE <USER_DEFINED, 20>
; PROCESSOR_INFO_2 DEFINE <J203, 800MHz, UPG_LIF_SOCKET>
; PROCESSOR_VOLTAGE_2 DEFINE <USER_DEFINED, 18>
;
; PROCESSOR_INFO_3 DEFINE <J204, 800MHz, UPG_SLOT1>
; PROCESSOR_VOLTAGE_3 DEFINE <USER_DEFINED, 22>
;
; PROCESSOR_INFO_4 DEFINE <J205, 800MHz, UPG_LIF_SOCKET>
; PROCESSOR_VOLTAGE_4 DEFINE <USER_DEFINED, 24>
;Processor cache info
;--------------------
NUMBER_OF_PROC_CACHE = 1
PROC_CACHE_INFO_L1 DEFINE <32KB, 32KB, CH_SYNCHRONOUS>
PROC_CACHE_CFG_L1 DEFINE <L1 Cache, CACHE_ENABLED, WRITE_BACK, INTERNAL, L1>
PROC_CACHE_CHAR_L1 DEFINE <40, SR_NONE, SCT_UNIFIED, CA_4WAY_ASSOC>
;----------------------------------------;
; MEMORY CONTROLLER ERRORDETECTING METHOD;
;----------------------------------------;------------------------------;
; Following enumerates describes Memory Controller error ;
; detecting method. At any given time only one value can be ;
; selected. Use left-hand-side key word to describe: ;
; Memory controller error detecting method ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
; MC_OTHER....................... Other ;
; MC_UNKNOWN..................... Unknown ;
; MC_NONE........................ None ;
; MC_8BIT_PARITY................. 8-bit Parity type ;
; MC_32BIT_ECC................... 32-bit ECC type ;
; MC_64BIT_ECC................... 64-bit ECC type ;
; MC_128BIT_ECC.................. 128-bit ECC type ;
; MC_CRC......................... CRC type ;
;-----------------------------------------------------------------------;
MEM_CTRL_EDD = MC_None
;----------------------;
; MEMORY CONTROLLER ECC;
;----------------------;------------------------------------------------;
; Following bit fields describes Memory Controller error ;
; correcting capability. At any given time more than on ;
; e value can be selected. set right-hand-side flags to ;
; describe: ;
; Memory controller error correcting capability ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
MCE_OTHER = 0 ; Other
MCE_UNKNOWN = 0 ; Unknown
MCE_NONE = 1 ; None
MCE_SINGLE_BIT_ECC = 0 ; Single bit ECC
MCE_DOUBLE_BIT_ECC = 0 ; Double bit ECC
MCE_ERROR_SCRUBBING = 0 ; Error scrubbing
;-------------------------------------;
; MEMORY CONTROLLER INTERLEAVE SUPPORT;
;-------------------------------------;---------------------------------;
; Following enumerates describes Memory Controller ;
; interleave support. At any given time only one ;
; value can be selected. Use left-hand-side keyword ;
; to describe: ;
; Memory Controller Interleave support ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
; IS_OTHER....................... Other ;
; IS_UNKNOWN..................... Unknown ;
; IS_ONEWAY_INTLEAVE............. Oneway interleave support ;
; IS_TWOWAY_INTLEAVE............. Twoway interleave support ;
; IS_FORWAY_INTLEAVE............. Fourway interleave support ;
; IS_EHTWAY_INTLEAVE............. Eightway interleave support ;
; IS_STNWAY_INTLEAVE............. Sixtenway interleave support ;
;-----------------------------------------------------------------------;
MEM_CTRL_INTRLV = IS_ONEWAY_INTLEAVE
;------------------------;
; MEMORY CONTROLLER SPEED;
;------------------------;----------------------------------------------;
; Following bit fields describes Memory Controller speed. ;
; At any given time more than one value can be selected. ;
; set right-hand-side flags to describe: ;
; Memory controller speed ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
SS_OTHER = No
SS_UNKNOWN = Yes
SS_70NS = No
SS_60NS = No
SS_50NS = No
;-----------------------------;
; MEMORY MODULE VOTAGE SUPPORT;
;-----------------------------;-----------------------------------------;
; Following bit fields describes Memory Module voltage. ;
; At any given time more than one value can be selected. ;
; set right-hand-side flags to describe: ;
; Memory module voltage support ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
MM_VOLTAGE_29V = 0
MM_VOLTAGE_33V = 1
MM_VOLTAGE_5V = 0
;-----------------------------------------------------------------------;
MEM_CTRL_INFO = Present
NUMBER_OF_MEM_MODULE = 3
MAX_MEM_MODULE_SIZE = 512MB
;-----------------------------;
; MEMORY MODULE SUPPORTED TYPE;
;-----------------------------;-----------------------------------------;
; Following bit fields describes Memory Module supported ;
; type. At any given time more than one value can be selected. ;
; set right-hand-side flags to describe: ;
; Memory module supported type ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
MM_TYPE_OTHER = 0 ; Other type
MM_TYPE_UNKNOWN = 0 ; Unknown type
MM_TYPE_STANDARD = 0 ; Standard type
MM_TYPE_FAST_PAGE_MODE = 0 ; Fast page mode type
MM_TYPE_EDO = 0 ; EDO type
MM_TYPE_PARITY = 0 ; Parity type
MM_TYPE_ECC = 0 ; ECC type
MM_TYPE_SIMM = 0 ; SIMM type
MM_TYPE_DIMM = 1 ; DIMM type
MM_TYPE_BURST_EDO = 0 ; BURST EDO type
MM_TYPE_SDRAM = 1 ; SDRAM type
;-----------------------------------------------------------------------;
MEM_MODULE_INFO = Present
MEMORY_TYPE_1 DEFINE <MM_TYPE_DIMM>
MEMORY_INFO_1 DEFINE <DIMM1, RAS_1, RAS_2, 60ns, 64MB, 64MB, MM_SINGLE_BANK>
MEMORY_ERR_1 DEFINE <0>
MEMORY_TYPE_2 DEFINE <MM_TYPE_DIMM>
MEMORY_INFO_2 DEFINE <DIMM2, RAS_3, RAS_4, 50ns,128MB, 128MB, MM_DOUBLE_BANK>
MEMORY_ERR_2 DEFINE <0>
MEMORY_TYPE_3 DEFINE <MM_TYPE_DIMM>
MEMORY_INFO_3 DEFINE <DIMM3, RAS_5, RAS_6, 60ns, 64MB, 64MB, MM_DOUBLE_BANK>
MEMORY_ERR_3 DEFINE <0>
; MEMORY_TYPE_4 DEFINE <MM_TYPE_DIMM>
; MEMORY_INFO_4 DEFINE <DIMM4, RAS_7, RAS_8, 70ns, 64MB, 64MB, MM_SINGLE_BANK>
; MEMORY_ERR_4 DEFINE <0>
;------------;
; CACHE TYPE ;
;------------;----------------------------------------------------------;
; Following bit fields describes Supported Cache tpye. ;
; At any given time more than one value can be selected. ;
; set right-hand-side flags to describe: ;
; Cache Type Suppoted ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
;
; CH_OTHER = 0 ; Other type of Cache
; CH_UNKNOWN = 0 ; Unknown type
; CH_NON_BURST = 0 ; Non Burst type
; CH_BURST = 1 ; Burst type
; CH_PIPELINE_BURST = 0 ; Pipeline Burst
; CH_SYNCHRONOUS = 0 ; Synchronous type
; CH_ASYNCHRONOUS = 0 ; Asynchronous type
;----------;------------------------------------------------------------;
; Following enumerates describes Cache Error Correcting ;
; capability. At any given time only one value can be ;
; selected. Use right-hand-side keywords to describe: ;
; Cache error correcting capability ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
; SR_OTHER....................... Other ;
; SR_UNKNOWN..................... Unknown ;
; SR_NONE........................ None ;
; SR_PARITY...................... Parity type ;
; SR_SINGLEBIT_ECC............... Single bit ECC ;
; SR_MULTIBIT_ECC................ Multibit ECC ;
;------------------;----------------------------------------------------;
; Following enumerates describes System Cache Type. At ;
; any given time only one value can be selected. Use ;
; left-hand-side keywords to describe: ;
; Memory controller error correcting capability ;
;-----------------------------------------------------------------------;
; Keywords to use Description ;
; --------------- ----------- ;
; ;
; SCT_OTHER...................... Other ;
; SCT_UNKNOWN.................... Unknown ;
; SCT_INSTRUCTION................ Instruction type ;
; SCT_DATA....................... Data type ;
; SCT_UNIFIED.................... Unified type ;
;-----------------------------------------------------------------------;
; Following enumerates describes Cache Associativity ;
; At any given time only one value can be selected. ;
; Use left-hand-side keywords to describe: ;
; Cache Associativity ;
;-----------------------------------------------------------------------;
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