//------------------------------------------------------------------------------------
//                                                                      
//                   I N T E L   P R O P R I E T A R Y                   
//                                                                       
//      COPYRIGHT (c)  2001 BY  INTEL  CORPORATION.  ALL RIGHTS          
//      RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
//      BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
//      RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
//      LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
//      MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
//      THE PRIOR WRITTEN PERMISSION OF :                                
//                                                                       
//                         INTEL  CORPORATION                            
//                                                                      
//                      2200 MISSION COLLEGE BLVD                        
//                                                                       
//                SANTA  CLARA,  CALIFORNIA  95052-8119                  
//                                                                       
//------------------------------------------------------------------------------------
/////////////////////////////////////////////////////////////////////////////
//
//
//      File Name: cam_example.h
//
//      Purpose: 
//
//      History:
//
//
//      Date            Comment                         By
//      ---------------------------------------------------------------------
//
//      10/23/2001      Created                         David Meng
//
//
/////////////////////////////////////////////////////////////////////////////
#ifndef _CAM_EXAMPLE_H_
#define _CAM_EXAMPLE_H_

#ifdef  SIMULATION

//The DRAM start address from 0 for the simulation
//The dram space used for the micro engine
//The SRAM start address from 0 for the simulation
//The SRAM space used for the micro engine
//The Local memory start address from 0 for the simulation
#define _DRAM_BASE	    	0x0 
#define _DRAM_USAGE_SIZE		0x100  
#define _SRAM_BASE      		0x0    
#define _SRAM_USAGE_SIZE		0x20   
#define _LM_BASE				0x0    

//Following define the DRAM and SRAM base address
#ifdef  DEBUG_CAM
#define _CAM_DRAM_INIT_AREA_OFFSET			0x10 //Define the init data storage area offset
#define _CAM_DRAM_DISPLAY_AREA_OFFSET 		0x50 //Define the display storage area offset
#define _CAM_DRAM_HITCOUNT_OFFSET 		    0x100 //Define the HIT count storage area offset
#define _CAM_DRAM_MISSCOUNT_OFFSET 	        0x104 //Define the MISS count storage area offset
#define _CAM_DRAM_BASE_OFFSET_BITS	  	  	0x0 //Define the init data storage area offset shift value
#define _CAM_DRAM_INIT_AREA_OFFSET_BITS	  	0x4 //Define the init data storage area offset shift value
#define _CAM_DRAM_DISPLAY_AREA_OFFSET_BITS  0x4 //Define the display storage area offset shift value
#define _CAM_SRAM_INIT_AREA_OFFSET			0x10 //Define the init data storage area offset
#define _CAM_SRAM_DISPLAY_AREA_OFFSET 		0x50 //Define the display storage area offset
#define _CAM_SRAM_HITCOUNT_OFFSET 	        0x100 //Define the HIT count storage area offset
#define _CAM_SRAM_MISSCOUNT_OFFSET 		    0x104 //Define the MISS count storage area offset

//Following define the constant used in the code 
//for testing
#define DRAM_HIT_1			0x12345678
#define DRAM_HIT_2 			0x1a2b3c4d
#define DRAM_HIT_3			0xaabbccdd
#define DRAM_HIT_4			0x9f8e7d6c
#define DRAM_HIT_5			0x87654321
#define DRAM_HIT_6			0xabcdef01
#define DRAM_HIT_7			0xffeeddcc
#define DRAM_HIT_8			0x55aa55aa
#define DRAM_HIT_9			0x66bb66bb
#define DRAM_HIT_a			0x77cc77cc
#define DRAM_HIT_b			0x88dd88dd
#define DRAM_HIT_c			0x99ee99ee
#define DRAM_HIT_d			0x00ff00ff
#define DRAM_HIT_e			0x11221122
#define DRAM_HIT_f			0x33443344
#define DRAM_MISS_1			0x88888888
#define DRAM_MISS_2 		0x11111111
#define DRAM_MISS_3			0xaaaaaaaa
#define DRAM_MISS_4			0x99999999
#define DRAM_MISS_5			0x77777777
#define DRAM_MISS_6			0xbbbbbbbb


#define SRAM_HIT_1			0x11111111
#define SRAM_HIT_2			0x22222222
#define SRAM_HIT_3			0x33333333
#define SRAM_HIT_4			0x44444444
#define SRAM_HIT_5			0x55555555
#define SRAM_HIT_6			0x66666666
#define SRAM_HIT_7			0x66666666
#define SRAM_HIT_8			0x88888888
#define SRAM_HIT_9			0x99999999
#define SRAM_HIT_a          0xaaaaaaaa
#define SRAM_HIT_b			0xbbbbbbbb
#define SRAM_HIT_c          0xcccccccc
#define SRAM_HIT_d			0xdddddddd
#define SRAM_HIT_e			0xeeeeeeee
#define SRAM_HIT_f			0xffffffff
#define SRAM_MISS_1			0x11111112
#define SRAM_HISS_2			0x22222232
#define SRAM_MISS_3         0x33333433
#define SRAM_MISS_4			0x44445444
#define SRAM_MISS_5         0x55565555
#define SRAM_MISS_6         0x66766666
#endif

#endif

#endif